公开(公告)号：US09474162B2

公开(公告)日：2016-10-18

申请号：US14151828

申请日：2014-01-10

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L21/00 ,  H05K3/00 ,  H05K1/09

CPC分类号： H05K3/007 ,  H05K1/097 ,  H05K2203/107

摘要： A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

摘要翻译： 电路互连衬底制造方法包括在载体的顶部上沉积第一层金属粉末，然后从第一层金属粉末形成第一层导电迹线。 然后将第二层金属粉末沉积到第一层导电迹线的至少一个区域上。 然后从第二层金属粉末形成第二层导电迹线，并且第二层的每个迹线电耦合到第一层的迹线。 将绝缘材料沉积到载体上以提供支撑迹线的绝缘基板。 该方法不需要使用任何湿化学品或化学蚀刻步骤。

公开(公告)号：US09437492B2

公开(公告)日：2016-09-06

申请号：US14499266

申请日：2014-09-29

申请人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

发明人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/83132 ,  H01L2224/85132 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

摘要翻译： 使用替代不同配置的半导体管芯组装半导体器件的方法使用相同的衬底面板。 所选择的配置的管芯被放置在阵列中，安装并连接到面板的第一面上的内部电接触焊盘，使用主要的基准标记和通常对应于不同替代的半导体管芯阵列的辅助基准标记阵列 配置 附属基准标记的间距等于面板上的内部电接触焊盘的相邻行之间的间隔，并且是管芯阵列的间距的次倍数。

公开(公告)号：US09401345B2

公开(公告)日：2016-07-26

申请号：US14474294

申请日：2014-09-01

申请人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Navas Khan Oratti Kalandar ,  Lan Chu Tan

IPC分类号： H05K7/10 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/03602 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L21/565 ,  H01L21/304 ,  H01L2224/83

摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.

摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。

公开(公告)号：US20160093533A1

公开(公告)日：2016-03-31

申请号：US14499266

申请日：2014-09-29

申请人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

发明人： Kai Yun Yow ,  Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L21/78 ,  H01L23/28 ,  H01L23/535 ,  H01L23/544 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/83132 ,  H01L2224/85132 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

摘要翻译： 使用替代不同配置的半导体管芯组装半导体器件的方法使用相同的衬底面板。 所选择的配置的管芯被放置在阵列中，安装并连接到面板的第一面上的内部电接触焊盘，使用主要的基准标记和通常对应于不同替代的半导体管芯阵列的辅助基准标记阵列 配置 附属基准标记的间距等于面板上的内部电接触焊盘的相邻行之间的间隔，并且是管芯阵列的间距的次倍数。

公开(公告)号：US09297713B2

公开(公告)日：2016-03-29

申请号：US14220121

申请日：2014-03-19

申请人： Wai Yew Lo ,  Lan Chu Tan

发明人： Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L29/84 ,  G01L9/00 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16 ,  H01L23/31 ,  H01L21/56

CPC分类号： G01L9/00 ,  G01L17/00 ,  G01L19/147 ,  G01L19/148 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/165 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/1624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92163 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014

摘要： A semiconductor pressure sensor device having a pressure-sensing die electrically connected to a microcontrol unit (MCU) using either through silicon vias (TSVs) or flip-chip bumps. An active surface of the pressure-sensing die is in facing relationship with the MCU. These embodiments avoid the need to used bonds to electrically connect the pressure-sensing die to the MCU, thereby saving time, reducing size, and reducing cost.

摘要翻译： 一种半导体压力传感器装置，其具有通过硅通孔（TSV）或倒装芯片凸块与微控制单元（MCU）电连接的压力感测管芯。 压敏传感芯片的有源表面与MCU面对关系。 这些实施例避免了使用键将电压连接到MCU的需要，从而节省时间，减小尺寸并降低成本。

公开(公告)号：US20160071789A1

公开(公告)日：2016-03-10

申请号：US14479377

申请日：2014-09-08

申请人： Pei Fan Tong ,  Boon Yew Low ,  Lan Chu Tan

发明人： Pei Fan Tong ,  Boon Yew Low ,  Lan Chu Tan

IPC分类号： H01L23/498 ,  H05K3/34 ,  H01L21/52 ,  H05K1/18 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K3/0014 ,  H05K3/0044 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/4046 ,  H05K3/4688 ,  H05K2201/09118 ,  H05K2201/10242 ,  H05K2201/10378 ,  H05K2203/0235

摘要： A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.

摘要翻译： 一种用于形成封装半导体器件的中介层的贯穿层的方法，其中导电结构在壳体的第一和第二端之间延伸。 然后将导电结构封装在模塑料中以形成模制棒，并将模制棒切片以获得穿透层。 穿通层具有导电孔，每个对应于一个导电结构的切片部分。 以这种方式形成的直通层的成本可能低于可比较的硅或玻璃直通层的成本。

公开(公告)号：US20150294924A1

公开(公告)日：2015-10-15

申请号：US14552497

申请日：2014-11-25

申请人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

发明人： Zhigang Bai ,  Jinzhong Yao ,  Lan Chu Tan

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/58 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

摘要翻译： 半导体封装包括具有第一类型的封装引线和预成型部分的第一引线框架型和具有围绕芯片焊盘并由预模制部分支撑的第二类型的封装引线的第二引线框架型 。 集成电路附接到管芯焊盘并且用接合线电连接到第一和第二类型的引线。 形成模具帽的模具复合体覆盖第一和第二引线框架类型，集成电路和接合线。 第一引线框类型可以是QFP型，第二引线框类型可以是QFN型。

公开(公告)号：US20150200180A1

公开(公告)日：2015-07-16

申请号：US14151811

申请日：2014-01-10

申请人： Kee Cheong Fam ,  Mohd Rusli Ibrahim ,  Lan Chu Tan

发明人： Kee Cheong Fam ,  Mohd Rusli Ibrahim ,  Lan Chu Tan

IPC分类号： H01L23/00 ,  H01L29/84 ,  H01L21/56

CPC分类号： H01L24/83 ,  H01L21/56 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/29 ,  H01L24/45 ,  H01L29/84 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/92247 ,  H01L2924/11 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

摘要： A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.

摘要翻译： 压力传感器装置包括安装或形成在基底上的凝胶保持器。 凝胶保持器具有空腔，并且压力感测模具安装在腔体内。 模具电连接到一个或多个其它封装元件。 将压敏凝胶材料分配到空腔中以覆盖压力感测模具的有源区域。 将模具化合物施加在凝胶保持器外部的基板的上表面上。

公开(公告)号：US20150200177A1

公开(公告)日：2015-07-16

申请号：US14151833

申请日：2014-01-10

申请人： CHEE SENG FOONG ,  Lan Chu Tan

发明人： CHEE SENG FOONG ,  Lan Chu Tan

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/19 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/96 ,  H01L2224/02379 ,  H01L2224/03332 ,  H01L2224/0347 ,  H01L2224/03505 ,  H01L2224/03552 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

摘要： A semiconductor device is assembled where a signal redistribution layer is formed over a partially encapsulated semiconductor die. The distribution layer is formed by selectively coating a first electrical insulating layer over an active surface of the die and a surrounding portion of the encapsulation material, where die bonding pads on the active surface of the die are exposed through access apertures in the first electrical insulating layer. A layer of metallic powder is deposited onto the first insulating layer and then electrically conductive runners are formed from the layer of metallic powder. The runners are coated with a further electrical insulating layer. A mounting area of each runner is exposed through an external connection aperture. Solder balls may be attached to the mounting areas.

摘要翻译： 组装半导体器件，其中在部分封装的半导体管芯上形成信号再分配层。 分布层通过选择性地涂覆在管芯的有效表面上的第一电绝缘层和封装材料的周围部分形成，其中管芯的有效表面上的管芯接合焊盘通过第一电绝缘中的通孔露出 层。 将一层金属粉末沉积在第一绝缘层上，然后由金属粉末层形成导电流道。 跑步者涂覆有另外的电绝缘层。 每个赛跑者的安装区域通过外部连接孔露出。 焊球可以附接到安装区域。

公开(公告)号：US09053972B1

公开(公告)日：2015-06-09

申请号：US14086932

申请日：2013-11-21

申请人： Chee Seng Foong ,  Lan Chu Tan

发明人： Chee Seng Foong ,  Lan Chu Tan

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03552 ,  H01L2224/0381 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11505 ,  H01L2224/11552 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01074 ,  H01L2924/01024 ,  H01L2224/11442 ,  H01L2924/014 ,  H01L2924/00

摘要： A pillar bump, such as a copper pillar bump, is formed on an integrated circuit chip by applying a metallic powder over a conductive pad on a surface of the chip. The metallic powder is selectively spot-lasered to form the pillar bump. Any remaining unsolidified metallic powder may be removed from the surface of the chip. This process may be repeated to increase the bump height. Further, a solder cap may be formed on an outer surface of the pillar bump.

摘要翻译： 通过在芯片的表面上的导电焊盘上施加金属粉末，在集成电路芯片上形成诸如铜柱凸起的柱状凸块。 选择性地点燃金属粉末以形成柱状凸块。 任何剩余的非固化金属粉末可以从芯片的表面去除。 可以重复该过程以增加凸起高度。 此外，可以在柱状凸起的外表面上形成焊锡帽。