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公开(公告)号：US20160064356A1
公开(公告)日：2016-03-03
申请号：US14474294
申请日：2014-09-01
IPC分类号： H01L25/065 , H01L23/498 , H01L21/768 , H01L23/00 , H01L21/48
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/6835 , H01L21/76877 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2221/68345 , H01L2221/68381 , H01L2224/03602 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/83424 , H01L2224/83447 , H01L2224/92 , H01L2924/18161 , H01L2924/351 , H01L2924/3512 , H01L2924/381 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L21/565 , H01L21/304 , H01L2224/83
摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.
摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。
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公开(公告)号：US20150054099A1
公开(公告)日：2015-02-26
申请号：US13975359
申请日：2013-08-25
CPC分类号： H01L21/56 , G01L19/147 , H01L21/50 , H01L23/24 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/73265 , H01L2224/83855 , H01L2924/16315 , H01L2924/1815 , H01L2924/00014 , H01L2924/00012 , H01L2924/00011 , H01L2924/0665
摘要： A semiconductor sensor device is assembled using a pre-molded lead frame having first and second die flags. The first die flag includes a cavity. A pressure sensor die (P-cell) is mounted within the cavity and a master control unit die (MCU) is mounted to the second flag. The P-cell and MCU are electrically connected to leads of the lead frame with bond wires. The die attach and wire bonding steps are each done in a single pass. A mold pin is placed over the P-cell and then the MCU is encapsulated with a mold compound. The mold pin is removed leaving a recess that is next filled with a gel material. Finally a lid is placed over the P-cell and gel material. The lid includes a hole that that exposes the gel-covered active region of the pressure sensor die to ambient atmospheric pressure outside the sensor device.
摘要翻译： 使用具有第一和第二管芯标记的预模制引线框组装半导体传感器装置。 第一个模具标志包括一个空腔。 压力传感器管芯（P-cell）安装在腔内，并且主控单元管芯（MCU）安装到第二标志上。 P单元和MCU通过接合线电连接到引线框架的引线。 芯片连接和引线键合步骤都是单次完成的。 模具销放置在P型电池上，然后用模具化合物封装MCU。 去除模具销，留下下一个填充有凝胶材料的凹槽。 最后将盖子放置在P细胞和凝胶材料上。 盖子包括孔，该孔将压力传感器芯片的凝胶覆盖的有源区域暴露于传感器装置外部的环境大气压力。
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公开(公告)号：US09401345B2
公开(公告)日：2016-07-26
申请号：US14474294
申请日：2014-09-01
IPC分类号： H05K7/10 , H01L25/065 , H01L23/00 , H01L21/48 , H01L21/768 , H01L23/498
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/6835 , H01L21/76877 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2221/68345 , H01L2221/68381 , H01L2224/03602 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/83424 , H01L2224/83447 , H01L2224/92 , H01L2924/18161 , H01L2924/351 , H01L2924/3512 , H01L2924/381 , H01L2924/014 , H01L2924/00014 , H01L2224/81 , H01L21/565 , H01L21/304 , H01L2224/83
摘要： A method of making an integrated circuit package, such as a ball grid array, includes providing a flexible tape that has first and second sets of bond pads on respective first and second surfaces thereof. A carrier is attached to the first surface of the flexible tape. Then conductive pillars are formed on the second set of bond pads and an intermediate layer of polymeric compound is deposited on the second surface of the flexible tape. After the compound has cured, a surface of the intermediate layer is ground to expose ends of the conductive pillars to form a sub-assembly comprising the flexible tape and the intermediate layer. Then the carrier is removed from the sub-assembly, thereby creating an interposer. The interposer is attached to a substrate and at least one die is attached to the interposer.
摘要翻译： 制造诸如球栅阵列的集成电路封装的方法包括提供在其相应的第一和第二表面上具有第一组和第二组接合焊盘的柔性带。 载体附接到柔性带的第一表面。 然后在第二组接合焊盘上形成导电柱，并且在柔性带的第二表面上沉积聚合物化合物的中间层。 在化合物固化之后，研磨中间层的表面以暴露导电柱的端部以形成包括柔性带和中间层的子组件。 然后从子组件移除载体，从而形成插入件。 插入器附接到衬底，并且至少一个管芯附接到插入器。
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公开(公告)号：US20150187728A1
公开(公告)日：2015-07-02
申请号：US14141465
申请日：2013-12-27
IPC分类号： H01L23/00
CPC分类号： H01L24/03 , H01L23/5286 , H01L23/5328 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05553 , H01L2224/06135 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/14 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207
摘要： In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.
摘要翻译： 在封装半导体器件中，裸片安装在具有电源连接焊盘的基板上。 管芯的外部（例如顶部）表面具有电力接合焊盘和分布式馈电焊盘。 接合线将衬底的电源连接焊盘电连接到管芯的电源接合焊盘，并且外部导电结构将管芯的功率接合焊盘电连接到管芯的分布式馈电焊盘。 外部导电结构被印刷或粘贴到外部模具表面上。 使用外部导电结构代替内部导电迹线（在管芯中）可以降低电阻功率损耗，并释放更多的内部管芯层内路由信号的空间。
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5.发明授权公开(公告)号：US08669140B1
公开(公告)日：2014-03-11
申请号：US13857143
申请日：2013-04-04
CPC分类号： H01L24/20 , H01L21/568 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/19 , H01L2224/221 , H01L2224/2518 , H01L2224/2919 , H01L2224/32135 , H01L2224/32145 , H01L2224/45144 , H01L2224/48228 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/81192 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2224/48227 , H01L2924/00012 , H01L2924/00 , H01L2224/83005
摘要： A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.
摘要翻译： 制造半导体器件的方法包括提供具有至少一个导电通孔的第一半导体管芯和导电框架构件。 形成第一封装层。 第一再分配层与第一封装层相对地形成。 形成与第一再分配层相对的第二再分配层。 第二半导体管芯安装并与第二再分配层中的接收器焊盘电连接。 第三半导体管芯安装到第二半导体管芯并且与接合线电连接到第二再分配层中的导体。 第二封装层将第二和第三半导体管芯，导线和导体嵌入第二再分布层。
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公开(公告)号：US20140021621A1
公开(公告)日：2014-01-23
申请号：US13550627
申请日：2012-07-17
CPC分类号： H01L24/49 , H01L23/3121 , H01L23/49531 , H01L23/49827 , H01L24/48 , H01L2224/05554 , H01L2224/48247 , H01L2224/49 , H01L2924/00014 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.
摘要翻译： 封装的半导体管芯具有安装到具有外部连接器的管芯支撑件的管芯支撑安装表面。 与管芯支撑安装表面相对的管芯连接焊盘表面具有作为半导体管芯的电路节点的相关联的管芯连接焊盘。 管芯连接焊盘表面还具有电源轨焊盘。 电源轨焊盘的表面积大于管芯连接焊盘的表面积。 接合线将电源轨焊盘电耦合到两个或更多个管芯连接焊盘。
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公开(公告)号：US20130344656A1
公开(公告)日：2013-12-26
申请号：US13530117
申请日：2012-06-22
IPC分类号： H01L21/78
CPC分类号： H01L21/561 , H01L21/486 , H01L21/568 , H01L23/142 , H01L23/3128 , H01L23/3735 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/16225 , H01L2224/73267 , H01L2224/9222 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/181 , H01L2224/83 , H01L2924/00
摘要： A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.
摘要翻译： 一种组装半导体器件的方法包括提供一种结构，其包括除了孔阵列之外的导电框架构件的阵列和在第一面处暴露并朝向第二面延伸的导电通孔阵列。 一组半导体管芯位于孔阵列中，其主动面位于结构的第一面。 组件从结构的第二面被封装，并且在结构的第一面和模具的有效面上形成再分布层。 从封装阵列的背面去除材料以暴露在背面的通孔，用于通过形成在背面上的另一重新分配层与垂直堆叠在再分布层上的电子部件连接。
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公开(公告)号：US08853058B2
公开(公告)日：2014-10-07
申请号：US13530117
申请日：2012-06-22
IPC分类号： H01L21/00
CPC分类号： H01L21/561 , H01L21/486 , H01L21/568 , H01L23/142 , H01L23/3128 , H01L23/3735 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/16225 , H01L2224/73267 , H01L2224/9222 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/181 , H01L2224/83 , H01L2924/00
摘要： A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.
摘要翻译： 一种组装半导体器件的方法包括提供一种结构，其包括除了孔阵列之外的导电框架构件的阵列和在第一面处暴露并朝向第二面延伸的导电通孔阵列。 一组半导体管芯位于孔阵列中，其主动面位于结构的第一面。 组件从结构的第二面被封装，并且在结构的第一面和模具的有效面上形成再分布层。 从封装阵列的背面去除材料以暴露在背面的通孔，用于通过形成在背面上的另一重新分配层与垂直堆叠在再分布层上的电子部件连接。
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公开(公告)号：US08643189B1
公开(公告)日：2014-02-04
申请号：US13550627
申请日：2012-07-17
CPC分类号： H01L24/49 , H01L23/3121 , H01L23/49531 , H01L23/49827 , H01L24/48 , H01L2224/05554 , H01L2224/48247 , H01L2224/49 , H01L2924/00014 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.
摘要翻译： 封装的半导体管芯具有安装到具有外部连接器的管芯支撑件的管芯支撑安装表面。 与管芯支撑安装表面相对的管芯连接焊盘表面具有作为半导体管芯的电路节点的相关联的管芯连接焊盘。 管芯连接焊盘表面还具有电源轨焊盘。 电源轨焊盘的表面积大于管芯连接焊盘的表面积。 接合线将电源轨焊盘电耦合到两个或更多个管芯连接焊盘。
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公开(公告)号：US09202770B1
公开(公告)日：2015-12-01
申请号：US14474291
申请日：2014-09-01
申请人： Chee Seng Foong , Lan Chu Tan
发明人： Chee Seng Foong , Lan Chu Tan
IPC分类号： H01L23/367 , H01L21/56 , B29B9/12
CPC分类号： H01L23/3675 , B29B9/12 , B29C45/02 , B29C45/14655 , B29C45/1634 , B29C45/1671 , B29C45/462 , H01L21/565 , H01L23/3128 , H01L23/3737 , H01L23/4334 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A packaged semiconductor device has an integrated circuit (IC) die and first and second volumes of molding compound. The first volume of molding compound is disposed on a first portion of a first side of the IC die and comprises a first molding compound. The second volume of molding compound is disposed on a second side of the IC die, different from the first side, and comprises a second molding compound, different from the first molding compound. By including different molding compounds, the properties of the packaged semiconductor device can be varied across the device.
摘要翻译： 封装的半导体器件具有集成电路（IC）模具和第一和第二体积的模塑料。 第一体积的模塑料被设置在IC模头的第一侧的第一部分上并且包括第一模塑料。 第二体积的成型化合物设置在IC模具的与第一侧不同的第二侧上，并且包括与第一模塑料不同的第二模塑料。 通过包括不同的成型化合物，封装的半导体器件的性能可以在整个器件上变化。
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