公开(公告)号：US20240332241A1

公开(公告)日：2024-10-03

申请号：US18744174

申请日：2024-06-14

Applicant: SK hynix Inc.

Inventor： Jin Woong KIM ,  Mi Seon LEE

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/30 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05186 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/14134 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2746 ,  H01L2224/29012 ,  H01L2224/29035 ,  H01L2224/29147 ,  H01L2224/29186 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3015 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/30517 ,  H01L2224/30519 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/81201 ,  H01L2224/83048 ,  H01L2224/83201 ,  H01L2924/04941 ,  H01L2924/05042

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

公开(公告)号：US20240304537A1

公开(公告)日：2024-09-12

申请号：US18584148

申请日：2024-02-22

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Motohito HORI ,  Yoshinari IKEDA ,  Akira HIRAO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/49844 ,  H01L23/49822 ,  H01L24/30 ,  H01L24/32 ,  H01L25/072 ,  H01L25/50 ,  H01L23/367 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2924/13091

Abstract: An electronic device, including: a conductive element having a conductive region on a front surface thereof; a fixing element having a fixing region on a front surface thereof, the fixing element being located apart from the conductive element in a plan view of the electronic device; and a wiring member having a flat plate shape. The wiring member includes a first portion bonded to the conductive region of the conductive element, a second portion fixed to the fixing region of the fixing element, and an inclined portion between the first portion and the second portion, the inclined portion being elastically deformable. In a side view of the electronic device, the conductive region of the conductive element and the fixing region of the fixing element are at different heights in a thickness direction of the electronic device.

公开(公告)号：US11948908B2

公开(公告)日：2024-04-02

申请号：US17304566

申请日：2021-06-23

Applicant: Japan Display Inc.

Inventor： Kazuyuki Yamada

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/30 ,  H01L24/83 ,  H01L25/167 ,  H01L24/29 ,  H01L24/32 ,  H01L24/98 ,  H01L2224/29286 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29339 ,  H01L2224/3003 ,  H01L2224/32145 ,  H01L2224/83052 ,  H01L2224/83986 ,  H01L2924/12041

Abstract: An electronic device comprising: an array substrate having a first electrode and a second electrode; a first connecting member arranged on the first electrode; a first LED chip mounted on the first connecting member; a second connecting member arranged on the second electrode and being thicker than the first connecting member; and a second LED chip mounted on the second connecting member. A distance from a reference surface of the array substrate to a top surface of the second connecting member is larger than a distance from the reference surface to a top surface of the first connecting member.

公开(公告)号：US20180358319A1

公开(公告)日：2018-12-13

申请号：US16107966

申请日：2018-08-21

Applicant: Mitsubishi Electric Corporation

Inventor： Daisuke MURATA ,  Yuji IMOTO

IPC: H01L23/00 ,  H01L23/492 ,  H01L25/07 ,  H01L23/31

CPC classification number: H01L24/29 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/562 ,  H01L24/27 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/40 ,  H01L24/83 ,  H01L24/84 ,  H01L25/072 ,  H01L2224/27013 ,  H01L2224/2746 ,  H01L2224/29082 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/3003 ,  H01L2224/32245 ,  H01L2224/33 ,  H01L2224/33181 ,  H01L2224/37099 ,  H01L2224/40137 ,  H01L2224/83385 ,  H01L2224/83444 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3656 ,  H01L2924/00012

Abstract: A semiconductor device includes: an insulating substrate; an aluminum pattern made of a pure aluminum or alloy aluminum material and formed on the insulating substrate; a plating formed on a surface of the aluminum pattern; and a semiconductor element joined to the plating, wherein a thickness of the plating is 10 μm or more.

公开(公告)号：US10083942B2

公开(公告)日：2018-09-25

申请号：US15524032

申请日：2015-11-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Bastien Letowski ,  Jean-Christophe Crebier ,  Nicolas Rouger ,  Julie Widiez

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/07 ,  H01L23/367 ,  H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L25/071 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/49805 ,  H01L24/26 ,  H01L24/32 ,  H01L25/072 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/3003 ,  H01L2224/3012 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19101 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

公开(公告)号：US20170338208A1

公开(公告)日：2017-11-23

申请号：US15524032

申请日：2015-11-03

Applicant: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE

Inventor： Bastien LETOWSKI ,  Jean-Christophe CREBIER ,  Nicolas ROUGER ,  Julie WIDIEZ

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L25/071 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3735 ,  H01L23/49805 ,  H01L24/26 ,  H01L24/32 ,  H01L25/072 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/29013 ,  H01L2224/291 ,  H01L2224/3003 ,  H01L2224/3012 ,  H01L2224/32141 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19101 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

公开(公告)号：US09768089B2

公开(公告)日：2017-09-19

申请号：US15224680

申请日：2016-08-01

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ranjan Rajoo ,  Kai Chong Chan

IPC: H01L23/10 ,  H01L21/683 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/10 ,  H01L21/561 ,  H01L21/6835 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/04042 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/245 ,  H01L2224/2732 ,  H01L2224/2741 ,  H01L2224/2745 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/2761 ,  H01L2224/27618 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29078 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/3012 ,  H01L2224/30505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/8389 ,  H01L2224/83905 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0105 ,  H01L21/304

Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

公开(公告)号：US09508679B2

公开(公告)日：2016-11-29

申请号：US14420181

申请日：2013-03-11

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Mitsuhiko Ueda ,  Yoshiharu Sanagawa ,  Takanori Aketa ,  Shintaro Hayashi

IPC: H01L23/00 ,  B23K20/00 ,  H01L21/52 ,  H01L21/683

CPC classification number: H01L24/97 ,  B23K20/00 ,  H01L21/52 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/04026 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75901 ,  H01L2224/7598 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/8309 ,  H01L2224/83123 ,  H01L2224/83127 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83805 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83906 ,  H01L2224/83907 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A mounting method of mounting chips on a substrate includes a temporarily-bonding process, and a main-bonding process. Temporarily-bonding process is to perform a first basic process, repeatedly depending on the number of the chips. First basic process includes a first step and a second step. First step is to align, on a first metal layer of the substrate, a second metal layer of each chip. Second step is to temporarily bond each chip by subjecting the first and second metal layers to solid phase diffusion bonding. Main-bonding process is to perform a second basic process, repeatedly depending on the number of the chips. Second basic process includes a third step and a fourth step. Third step is to recognize a position of each chip temporarily mounted on the substrate. Fourth step is to firmly bond each chip by subjecting the first and second metal layers to liquid phase diffusion bonding.

Abstract translation: 将芯片安装在基板上的安装方法包括临时粘合工艺和主要粘结工艺。 暂时粘接过程是根据芯片的数量重复执行第一个基本过程。 第一基本过程包括第一步骤和第二步骤。 第一步是在衬底的第一金属层上对准每个芯片的第二金属层。 第二步是通过使第一和第二金属层进行固相扩散接合来临时粘合每个芯片。 主键合过程是根据芯片的数量重复执行第二个基本过程。 第二基本过程包括第三步骤和第四步骤。 第三步是识别临时安装在基板上的每个芯片的位置。 第四步是通过使第一和第二金属层进行液相扩散接合来牢固地结合每个芯片。

公开(公告)号：US09223202B2

公开(公告)日：2015-12-29

申请号：US11774710

申请日：2007-07-09

Applicant: Byung-Jin Choi ,  Sidlgata V. Sreenivasan ,  Carlton Grant Willson ,  Mattherw E. Colburn ,  Todd C. Bailey ,  John G. Ekerdt

Inventor： Byung-Jin Choi ,  Sidlgata V. Sreenivasan ,  Carlton Grant Willson ,  Mattherw E. Colburn ,  Todd C. Bailey ,  John G. Ekerdt

IPC: G03F7/00 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/16

CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/16 ,  G03F7/164 ,  H01L2224/29012 ,  H01L2224/3003 ,  H01L2224/3016 ,  H01L2924/01067 ,  H01L2924/1461 ,  H01L2924/00

Abstract: Disclosed herein is an automatic fluid dispensing method and system for dispensing fluid on the surface of a plate-like material, or substrate, including a semiconductor wafer for imprint lithography processes. The dispensing method uses fluid dispenser and a substrate stage that may generate relative lateral motions between a fluid dispenser tip a substrate. Also described herein are methods and devices for creating a planar surface on a substrate using a substantially unpatterned planar template.

Abstract translation: 本文公开了一种用于在板状材料或基板的表面上分配流体的自动流体分配方法和系统，其包括用于压印光刻工艺的半导体晶片。 分配方法使用流体分配器和可在流体分配器尖端基底之间产生相对侧向运动的基底台。 本文还描述了使用基本上未图案化的平面模板在衬底上创建平面表面的方法和装置。

公开(公告)号：US09159652B2

公开(公告)日：2015-10-13

申请号：US14183156

申请日：2014-02-18

Applicant: STMicroelectronics S.r.l.

Inventor： Concetto Privitera

IPC: H01L29/267 ,  H01L33/00 ,  H01L29/40 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/28 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76877 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2224/29034 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/32058 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/81121 ,  H01L2224/81192 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/81855 ,  H01L2224/83121 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/9201 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An electronic device is described comprising at least one chip enclosed in a package, in turn provided with a metallic structure or leadframe having a plurality of connection pins, this chip having at least one first contact realized on a first face and at least one second contact realized on a second and opposite face of this chip. The chip comprises at least one through via crossing the whole section of the chip as well as a metallic layer extending from the second contact arranged on the first face, along walls of the at least one through via up to the second and opposite face in correspondence with an additional pad. The electronic device comprises at least one interconnection layer for the electrical and mechanical connection between the chip and the metallic structure having at least one portion realized in correspondence with the at least one through via so as to bring the second contact placed on the second face of the chip back on its first face. An assembly process of such an electronic device is also described.

Abstract translation: 描述了一种电子设备，其包括封装在封装中的至少一个芯片，其又设置有具有多个连接引脚的金属结构或引线框架，该芯片具有在第一面上实现的至少一个第一触点和至少一个第二触点 在该芯片的第二个相对面上实现。 芯片包括穿过芯片的整个部分的至少一个通孔以及从布置在第一面上的第二触点延伸的金属层，沿着至少一个通孔的壁延伸到对应的第二和相对面 附加一个垫。 电子设备包括用于芯片和金属结构之间的电气和机械连接的至少一个互连层，其具有与至少一个通孔相对应地实现的至少一个部分，以便将第二接触件放置在第二面 芯片回到了第一张脸上。 还描述了这种电子设备的组装过程。