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公开(公告)号：US20240178165A1
公开(公告)日：2024-05-30
申请号：US18058932
申请日：2022-11-28
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： Ranjan Rajoo , Kai Chong Chan
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/45 , H01L24/13 , H01L2224/0239 , H01L2224/0381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05082 , H01L2224/05147 , H01L2224/05164 , H01L2224/05573 , H01L2224/05647 , H01L2224/05664 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/45147
Abstract: A structure includes a copper bond pad for copper interconnects that uses a conductive layer of palladium or copper palladium. The structure may include a substrate, and a copper bond pad over the substrate. A conductive layer is in direct contact with an upper surface of the copper bond pad. The conductive layer consists of palladium, copper palladium or both palladium and copper palladium. A copper interconnect is in direct contact with the conductive layer. The copper interconnect can be a copper wire bond or a copper redistribution layer (RDL) with a solder ball on the copper RDL. The structure provides high temperature reliability copper-to-copper interconnection by removing intermetallic compounds between the pad and copper interconnect.
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公开(公告)号：US11444045B2
公开(公告)日：2022-09-13
申请号：US16994644
申请日：2020-08-16
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ramasamy Chockalingam , Juan Boon Tan , Xiaodong Li , Kai Chong Chan , Ranjan Rajoo
Abstract: A semiconductor device is provided that includes a bond pad, an insulating layer, and a bonding structure. The bond pad is in a dielectric layer and the insulating layer is over the bond pad; the insulating layer having an opening over the bond pad formed therein. The bonding structure electrically couples the bond pad in the opening. The bonding structure has a height that at least extends to an upper surface of the insulating layer.
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公开(公告)号：US09768089B2
公开(公告)日：2017-09-19
申请号：US15224680
申请日：2016-08-01
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ranjan Rajoo , Kai Chong Chan
IPC: H01L23/10 , H01L21/683 , H01L21/56 , H01L23/00
CPC classification number: H01L23/10 , H01L21/561 , H01L21/6835 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2221/68327 , H01L2224/02311 , H01L2224/02331 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/03002 , H01L2224/04042 , H01L2224/13024 , H01L2224/131 , H01L2224/24051 , H01L2224/245 , H01L2224/2732 , H01L2224/2741 , H01L2224/2745 , H01L2224/27462 , H01L2224/27464 , H01L2224/2761 , H01L2224/27618 , H01L2224/29011 , H01L2224/29014 , H01L2224/29078 , H01L2224/29111 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/3003 , H01L2224/30051 , H01L2224/3012 , H01L2224/30505 , H01L2224/73103 , H01L2224/73203 , H01L2224/73267 , H01L2224/82101 , H01L2224/83065 , H01L2224/83075 , H01L2224/8309 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2224/83862 , H01L2224/83874 , H01L2224/8389 , H01L2224/83905 , H01L2224/92 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2924/01322 , H01L2924/1461 , H01L2924/00 , H01L2924/014 , H01L2224/83 , H01L2224/0231 , H01L2224/03 , H01L2224/11 , H01L2924/00014 , H01L2924/00012 , H01L2224/82 , H01L2924/01013 , H01L2924/01029 , H01L2924/01079 , H01L2924/0105 , H01L21/304
Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.
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公开(公告)号：US09761561B2
公开(公告)日：2017-09-12
申请号：US14660949
申请日：2015-03-18
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ranjan Rajoo , Kai Chong Chan
IPC: H01L21/304 , H01L25/065 , H01L25/00 , H01L21/768
CPC classification number: H01L25/0657 , H01L21/304 , H01L21/76898 , H01L24/08 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/08145 , H01L2224/32145 , H01L2224/33181 , H01L2224/73251 , H01L2224/80203 , H01L2224/8312 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2224/83862 , H01L2224/83874 , H01L2224/8389 , H01L2224/92 , H01L2224/9202 , H01L2224/9222 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/10156 , H01L2924/1461 , H01L2924/00014 , H01L2224/80 , H01L2224/83 , H01L2224/08 , H01L2224/32 , H01L2224/0231 , H01L2224/03 , H01L2224/11
Abstract: Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.
