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公开(公告)号：US12046573B2
公开(公告)日：2024-07-23
申请号：US17697708
申请日：2022-03-17
申请人： SK hynix Inc.
发明人： Jin Woong Kim , Mi Seon Lee
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/30 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04026 , H01L2224/05025 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05186 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/1146 , H01L2224/13014 , H01L2224/13025 , H01L2224/13147 , H01L2224/14134 , H01L2224/14181 , H01L2224/16146 , H01L2224/16238 , H01L2224/17181 , H01L2224/2746 , H01L2224/29012 , H01L2224/29035 , H01L2224/29147 , H01L2224/29186 , H01L2224/3003 , H01L2224/30051 , H01L2224/3015 , H01L2224/30181 , H01L2224/30505 , H01L2224/30517 , H01L2224/30519 , H01L2224/32145 , H01L2224/73104 , H01L2224/73153 , H01L2224/81201 , H01L2224/83048 , H01L2224/83201 , H01L2924/04941 , H01L2924/05042
摘要： A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.
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公开(公告)号：US20230299247A1
公开(公告)日：2023-09-21
申请号：US18058201
申请日：2022-11-22
发明人： Dong Hyun LEE , Si Joon SONG
CPC分类号： H01L33/60 , H01L23/562 , H01L24/29 , H01L24/83 , H01L25/167 , H01L24/30 , H01L24/32 , H01L2224/26122 , H01L2224/26155 , H01L2224/29016 , H01L2224/2919 , H01L2224/30517 , H01L2224/32155 , H01L2224/83007 , H01L2224/8322 , H01L2224/83874
摘要： A display device includes: a display layer on a substrate, the display layer including a light emitting element; a reflective structure on the display layer; a resin part on the display layer; a cover part on the resin part; and a driving circuit board, at least a portion of the driving circuit board being on a side of the display layer. The reflective structure includes a reflective surface facing the at least the portion of the driving circuit board.
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公开(公告)号：US20230387372A1
公开(公告)日：2023-11-30
申请号：US18205312
申请日：2023-06-02
发明人： Yoonsuk LEE , Eunhye KIM , Sangmoo PARK , Jamyeong KOO , Sera KWON , Byunghoon LEE , Changkyu CHUNG
CPC分类号： H01L33/62 , H01L25/167 , H01L33/58 , H01L24/29 , H01L24/30 , H01L24/32 , H01L2224/30505 , H01L2224/30517 , H01L2224/3003 , H01L2224/3011 , H01L2224/32145 , H01L2924/12041 , H01L2224/2919 , H01L2224/29111 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2924/0132
摘要： Provided is a display assembly including a plurality of light emitting diodes, a plurality of electrodes provided on the plurality of light emitting diodes, a substrate, a plurality of electrode pads provided on the substrate, the plurality of electrode pads being connected to the electrodes provided on the plurality of light emitting diodes, and an adhesive layer fixing the plurality of light emitting diodes to the substrate, wherein the adhesive layer includes a non-conductive polymer resin, a flux agent mixed with the non-conductive polymer resin, and a plurality of conductive particles dispersed in the non-conductive polymer resin and connecting the electrodes of the light emitting diodes and the plurality of electrode pads.
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公开(公告)号：US20230268308A1
公开(公告)日：2023-08-24
申请号：US18067617
申请日：2022-12-16
发明人： Gaius Gillman Fountain, JR. , Chandrasekhar Mandalapu , Cyprian Emeka Uzoh , Jeremy Alfred Theil
IPC分类号： H01L23/00
CPC分类号： H01L24/27 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/29 , H01L24/05 , H01L24/06 , H01L24/03 , H01L2224/83905 , H01L2224/27462 , H01L2224/27616 , H01L2224/29147 , H01L2224/29155 , H01L2224/29186 , H01L2224/30505 , H01L2224/3003 , H01L2224/30131 , H01L2224/3015 , H01L2224/30517 , H01L2224/32145 , H01L2224/83895 , H01L2224/83896 , H01L2224/80986 , H01L2224/80035 , H01L2224/80935 , H01L2224/05547 , H01L2224/05181 , H01L2224/06155 , H01L2224/06152 , H01L2224/80357 , H01L2224/80896 , H01L2224/08145 , H01L2224/0603 , H01L24/80 , H01L2224/03616 , H01L2224/05166 , H01L2224/06131 , H01L2224/80895 , H01L2224/03462 , H01L2224/80948 , H01L2224/05647 , H01L2224/06136 , H01L2224/05155
摘要： Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.
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公开(公告)号：US20240332241A1
公开(公告)日：2024-10-03
申请号：US18744174
申请日：2024-06-14
申请人： SK hynix Inc.
发明人： Jin Woong KIM , Mi Seon LEE
IPC分类号： H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L24/30 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0652 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04026 , H01L2224/05025 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05186 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/1146 , H01L2224/13014 , H01L2224/13025 , H01L2224/13147 , H01L2224/14134 , H01L2224/14181 , H01L2224/16146 , H01L2224/16238 , H01L2224/17181 , H01L2224/2746 , H01L2224/29012 , H01L2224/29035 , H01L2224/29147 , H01L2224/29186 , H01L2224/3003 , H01L2224/30051 , H01L2224/3015 , H01L2224/30181 , H01L2224/30505 , H01L2224/30517 , H01L2224/30519 , H01L2224/32145 , H01L2224/73104 , H01L2224/73153 , H01L2224/81201 , H01L2224/83048 , H01L2224/83201 , H01L2924/04941 , H01L2924/05042
摘要： A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.
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公开(公告)号：US20240222308A1
公开(公告)日：2024-07-04
申请号：US18149121
申请日：2023-01-02
申请人： PIXART IMAGING INC.
发明人： SAI-MUN LEE , CHEE-PIN T'NG
IPC分类号： H01L23/00
CPC分类号： H01L24/29 , H01L24/30 , H01L24/32 , H01L24/83 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/0603 , H01L2224/06155 , H01L2224/06181 , H01L2224/29007 , H01L2224/29013 , H01L2224/29015 , H01L2224/29021 , H01L2224/29023 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/3015 , H01L2224/30505 , H01L2224/30517 , H01L2224/32227 , H01L2224/48227 , H01L2224/4912 , H01L2224/73265 , H01L2224/83192 , H01L2924/0665
摘要： A sensor packaging method and a sensor package are provided. The method includes: providing a substrate having upper and lower board surfaces, in which the upper board surface has a die-bonding region. The substrate includes a core material layer, an upper metal layer, and an upper protection layer, a first window is formed to penetrate the upper protection layer and located at a periphery of the die-bonding region, and the first window is opened for a first ground electrode connected to a first ground portion. The method further includes: performing a dispensing step to apply an adhesive material on the upper board surface in at least a portion of the die-bonding region; and attaching a sensor die to the substrate through the adhesive material, in which the sensor die is disposed in the die-bonding region and has a first ground pin electrically connected to the first ground electrode.
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公开(公告)号：US20180218959A1
公开(公告)日：2018-08-02
申请号：US15877538
申请日：2018-01-23
申请人： JTEKT CORPORATION
发明人： Naoki TANI
IPC分类号： H01L23/36 , H01L29/423 , H05K1/02 , H01L23/488 , H01L23/538
CPC分类号： H01L23/36 , H01L23/488 , H01L23/5389 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/73 , H01L29/4238 , H01L2224/13013 , H01L2224/131 , H01L2224/14051 , H01L2224/14151 , H01L2224/14156 , H01L2224/14517 , H01L2224/16227 , H01L2224/16245 , H01L2224/29013 , H01L2224/291 , H01L2224/30051 , H01L2224/30151 , H01L2224/30156 , H01L2224/30517 , H01L2224/32014 , H01L2224/32245 , H01L2224/33051 , H01L2224/33181 , H01L2224/73253 , H01L2224/81801 , H01L2224/81825 , H01L2224/83801 , H01L2224/83825 , H01L2924/3511 , H02K9/22 , H02K11/33 , H05K1/0201 , H05K2201/10439 , H01L2924/014 , H01L2924/00012 , H01L2924/00014
摘要： An electrode surface of a horizontal semiconductor chip and a substrate are joined together through a plurality of first joint portions including a plurality of joint portions at which a plurality of electrodes formed on the electrode surface are joined to the substrate. A no-electrode surface of the horizontal semiconductor chip and a heatsink are joined together through a second joint portion at which the no-electrode surface and the heatsink are joined together. In a plan view from a direction normal to a principal surface of the substrate, when a region inside the outline of the rough shape of an aggregate of the first joint portions is a first joint region and a region inside the outline of the second joint portion is a second joint region, the first joint region and the second joint region are the same in position, shape, and size.
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