公开(公告)号：US09502388B2

公开(公告)日：2016-11-22

申请号：US15017666

申请日：2016-02-07

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H01L29/15 ,  H01L31/0312 ,  H01L25/07 ,  H01L21/82 ,  H01L27/02 ,  H01L27/088 ,  H01L23/495 ,  H01L29/16 ,  H01L27/06 ,  H01L29/808 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L25/072 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/3702 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/84

Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，形成在半导体芯片CHP1的前表面上的栅极焊盘GPj被布置成比其他引线（漏极引线DL和栅极引线GL）更靠近源极引线SL。 结果，根据本发明，可以缩短栅极焊盘GPj和源极引线SL之间的距离，从而可以缩短用于将栅极焊盘GPj和源极引线SL连接在一起的焊丝Wgj的长度。 因此，根据本发明，可以充分地减小存在于导线Wgj中的寄生电感。

公开(公告)号：US09048119B2

公开(公告)日：2015-06-02

申请号：US13909293

申请日：2013-06-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H03K17/60 ,  H01L27/088 ,  H01L29/16 ,  H03K3/012 ,  H03K17/10 ,  H03K17/567 ,  H01L29/78 ,  H01L23/495 ,  H03K17/687

CPC classification number: H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Abstract translation: 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制成具有将两个晶体管设置在OFF状态的周期。

公开(公告)号：US09960153B2

公开(公告)日：2018-05-01

申请号：US14733776

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Satoru Akiyama ,  Hiroyoshi Kobayashi ,  Hisao Inomata ,  Sei Saitou

IPC: H01L23/495 ,  H01L25/18 ,  H01L21/82 ,  H03F1/22 ,  H01L23/498 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L29/808 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/78 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2924/181 ,  H03F1/223 ,  H03F1/226 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

公开(公告)号：US09917078B2

公开(公告)日：2018-03-13

申请号：US14733776

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Satoru Akiyama ,  Hiroyoshi Kobayashi ,  Hisao Inomata ,  Sei Saitou

IPC: H01L23/495 ,  H01L25/18 ,  H01L21/82 ,  H03F1/22 ,  H01L23/498 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L29/808 ,  H01L23/31

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

公开(公告)号：US10607978B2

公开(公告)日：2020-03-31

申请号：US15894564

申请日：2018-02-12

Applicant: Renesas Electronics Corporation

Inventor： Satoru Akiyama ,  Hiroyoshi Kobayashi ,  Hisao Inomata ,  Sei Saitou

IPC: H01L25/18 ,  H01L23/495 ,  H01L21/82 ,  H03F1/22 ,  H01L23/498 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L29/808 ,  H01L23/31

Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.

公开(公告)号：US20160155726A1

公开(公告)日：2016-06-02

申请号：US15017666

申请日：2016-02-07

Applicant: Renesas Electronics Corporation

Inventor： Takamitsu Kanazawa ,  Satoru Akiyama

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/538 ,  H01L29/78 ,  H01L23/00 ,  H01L29/808 ,  H01L29/16

CPC classification number: H01L25/072 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/3701 ,  H01L2224/3702 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40105 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/84

Abstract: Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，形成在半导体芯片CHP1的前表面上的栅极焊盘GPj被布置成比其他引线（漏极引线DL和栅极引线GL）更靠近源极引线SL。 结果，根据本发明，可以缩短栅极焊盘GPj和源极引线SL之间的距离，从而可以缩短用于将栅极焊盘GPj和源极引线SL连接在一起的焊丝Wgj的长度。 因此，根据本发明，可以充分地减小存在于导线Wgj中的寄生电感。