Patent search cpc:"H01L2224/40155" Page 1

1.

发明申请
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
Title translation: 半导体器件及其制造方法

公开(公告)号：US20150137344A1

公开(公告)日：2015-05-21

申请号：US14543108

申请日：2014-11-17

Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI

Inventor： Shogo MORI , Yuri OTOBE , Shinsuke NISHI

IPC: H01L23/367 , H01L21/56 , H01L23/00 , H01L23/31

CPC classification number: H01L24/33 , H01L23/3121 , H01L23/36 , H01L23/3735 , H01L23/4334 , H01L23/473 , H01L23/49811 , H01L24/29 , H01L24/32 , H01L24/40 , H01L24/83 , H01L24/84 , H01L24/92 , H01L25/072 , H01L25/18 , H01L2224/291 , H01L2224/32227 , H01L2224/40095 , H01L2224/40105 , H01L2224/40155 , H01L2224/40225 , H01L2224/73263 , H01L2224/83801 , H01L2224/92246 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/37099

Abstract: A semiconductor device has a circuit board including an insulation layer, a wiring layer formed on one surface of the insulation layer, and a buffer layer formed on the other surface of the insulation layer, a semiconductor element bonded to the wiring layer, a radiator member bonded to the buffer layer of the circuit board, and a resin member to seal the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board. A method for manufacturing the semiconductor device includes bonding the buffer layer of the circuit board to the radiator member, bonding the semiconductor element to the wiring layer of the circuit board, and sealing the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board with resin after the two bonding steps.

Abstract translation: 半导体器件具有电路板，其包括绝缘层，形成在绝缘层的一个表面上的布线层和形成在绝缘层的另一个表面上的缓冲层，接合到布线层的半导体元件，散热器构件接合到电路板的缓冲层，以及树脂构件，用于密封半导体元件和包括电路板中的缓冲层的外周表面的电路板的整个表面。一种半导体装置的制造方法，其特征在于，将所述电路基板的缓冲层与所述散热部件接合，将所述半导体元件接合到所述电路基板的配线层，并将所述半导体元件和所述电路基板的整体表面电路板的缓冲层的周边表面与两个接合步骤之后的树脂。

2.

发明公开
DIRECT SUBSTRATE-SIDE COOLING IN POWER DEVICE MODULE 审中-公开

公开(公告)号：US20240038632A1

公开(公告)日：2024-02-01

申请号：US17814949

申请日：2022-07-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Atapol PRAJUCKAMOL , Chee Hiong CHEW , Yushuang YAO

IPC: H01L23/473 , H01L25/07 , H01L23/00 , H01L23/373 , H01L21/48

CPC classification number: H01L23/473 , H01L25/072 , H01L24/40 , H01L23/3735 , H01L21/4807 , H01L2224/40155 , H01L2924/10272 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091

Abstract: A method includes disposing at least one power device between a first direct bonded metal (DBM) substrate and a second DMB substrate and thermally coupling a plurality of pipes to a top side of the first DBM substrate opposite a side of the first DBM substrate with the at least one power device. The plurality of pipes is configured to carry cooling fluids in thermal contact with the first DBM substrate.

3.

发明申请
POWER MODULE 审中-公开

公开(公告)号：US20170352629A1

公开(公告)日：2017-12-07

申请号：US15537466

申请日：2015-09-29

Applicant: Mitsubishi Electric Corporation

Inventor： Akihisa FUKUMOTO , Tetsu NEGISHI , Kei YAMAMOTO , Toshiaki SHINOHARA , Kazuyasu NISHIKAWA

IPC: H01L23/00 , H01L23/373 , H01L23/29 , H01L23/31

CPC classification number: H01L23/562 , H01L23/051 , H01L23/293 , H01L23/3107 , H01L23/3114 , H01L23/3735 , H01L23/48 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/73 , H01L25/072 , H01L2224/29111 , H01L2224/29139 , H01L2224/29147 , H01L2224/29565 , H01L2224/29655 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/3754 , H01L2224/40095 , H01L2224/40137 , H01L2224/40155 , H01L2224/73213 , H01L2224/73263 , H01L2224/84801 , H01L2924/00014 , H01L2924/0002 , H01L2924/014 , H01L2924/181 , H01L2924/18301 , H01L2924/351 , H01L2924/00012 , H01L2924/00 , H01L2224/37099

Abstract: A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface.

4.

发明授权
Semiconductor device 有权

公开(公告)号：US12040301B2

公开(公告)日：2024-07-16

申请号：US17292878

申请日：2019-11-08

Applicant: ROHM CO., LTD.

Inventor： Katsuhiko Yoshihara

IPC: H01L23/00 , H01L23/495 , H01L23/52 , H01L25/07

CPC classification number: H01L24/40 , H01L23/49575 , H01L23/52 , H01L24/84 , H01L25/072 , H01L23/49537 , H01L23/49582 , H01L24/73 , H01L2224/40155 , H01L2224/40491 , H01L2224/40499 , H01L2224/405 , H01L2224/73221 , H01L2224/73263 , H01L2224/84214 , H01L2924/01402 , H01L2924/01403 , H01L2924/40252 , H01L2924/404

Abstract: Semiconductor device A1 of the present disclosure includes: semiconductor element 10 (semiconductor elements 10A and 10B) having element obverse face and element reverse face facing toward opposite sides in z direction; support substrate 20 supporting semiconductor element 10; conductive block 60 (first block 61 and second block 62) bonded to element obverse face via first conductive bonding material (block bonding materials 610 and 620); and metal member (lead member 40 and input terminal 32) electrically connected to semiconductor element 10 via conductive block 60. Conductive block 60 has a thermal expansion coefficient smaller than that of metal member. Conductive block 60 and metal member are bonded to each other by a weld portion (weld portions M4 and M2) at which a portion of conductive block 60 and a portion of metal member are welded to each other. Thus, the thermal cycle resistance can be improved.

5.

发明公开
SEMICONDUCTOR APPARATUS 审中-公开

公开(公告)号：US20240055355A1

公开(公告)日：2024-02-15

申请号：US18493325

申请日：2023-10-24

Applicant: ROHM CO., LTD.

Inventor： Ryuta WATANABE , Takukazu OTSUKA

IPC: H01L23/538 , H01L23/31 , H01L23/34

CPC classification number: H01L23/5383 , H01L23/3121 , H01L23/34 , H01L2224/40155 , H01L24/40

Abstract: A semiconductor device includes an insulation layer, a support layer located on the insulation layer and containing a metal, and a semiconductor element bonded to the support layer. The semiconductor element includes an element metal layer facing the support layer. A solid-phase diffusion bonding layer is interposed between the support layer and the element metal layer. The insulation layer is lower in Vickers hardness than the support layer.

6.

发明申请
SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件

公开(公告)号：US20170042053A1

公开(公告)日：2017-02-09

申请号：US15200890

申请日：2016-07-01

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shin SOYANO

IPC: H05K7/02 , H05K1/02 , H05K5/00 , H05K1/18 , H05K1/14

CPC classification number: H05K7/026 , H01L23/3142 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/83 , H01L24/84 , H01L24/92 , H01L25/07 , H01L2224/291 , H01L2224/29294 , H01L2224/293 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/3701 , H01L2224/37011 , H01L2224/37599 , H01L2224/401 , H01L2224/40137 , H01L2224/40155 , H01L2224/40499 , H01L2224/48227 , H01L2224/48472 , H01L2224/83801 , H01L2224/84801 , H01L2224/9221 , H01L2224/92246 , H01L2924/00014 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091 , H01L2924/15159 , H01L2924/15162 , H05K1/0263 , H05K1/0298 , H05K1/142 , H05K1/181 , H05K5/0004 , H05K5/0069 , H05K2201/049 , H05K2201/10166 , H05K2201/10174 , H05K2201/10363 , H05K2201/10522 , H01L2924/014 , H01L2224/45099 , H01L2924/00012 , H01L2224/83 , H01L2224/84 , H01L2224/37099

Abstract: In a semiconductor device, a multilayer substrate includes an insulating substrate, a first circuit board having a first semiconductor chip disposed thereon, and a second circuit board having a second semiconductor chip disposed thereon. On the multilayer substrate of the semiconductor device, a plate portion of a resin plate including a first positioning portion that regulates the position of each semiconductor chip is sandwiched between a first jumper terminal, which includes a first terminal connected to the first semiconductor chip and a first plate member perpendicular to the first terminal, and a second jumper terminal, which includes a second terminal connected to the second semiconductor chip and a second plate member perpendicular to the second terminal.

Abstract translation: 在半导体器件中，多层基板包括绝缘基板，具有设置在其上的第一半导体芯片的第一电路板和设置在其上的第二半导体芯片的第二电路板。在半导体装置的多层基板上，包括调整各半导体芯片的位置的第一定位部的树脂板的板部夹在包括与第一半导体芯片连接的第一端子的第一跨接端子和垂直于第一端子的第一板构件和第二跨接端子，其包括连接到第二半导体芯片的第二端子和垂直于第二端子的第二板构件。

7.

发明公开
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING RIBBON, APPARATUS AND DEVICE 审中-公开

公开(公告)号：US20240250058A1

公开(公告)日：2024-07-25

申请号：US18416079

申请日：2024-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Mauro MAZZOLA , Fabio MARCHISI

IPC: H01L23/00 , H01L23/498 , H01L25/00 , H01L25/065

CPC classification number: H01L24/40 , H01L23/49838 , H01L24/35 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/50 , H01L2224/355 , H01L2224/40155 , H01L2224/48155 , H01L2224/73221 , H01L2924/153

Abstract: A semiconductor die is arranged at a die mounting location of a substrate. The substrate includes an array of electrically conductive leads at the periphery of the substrate. Electrical coupling is provided between the semiconductor die and selected ones of the electrically conductive leads in the array of electrically conductive leads via electrically conductive ribbons. Each ribbon has a body portion with a first width as well as first and second end portions bonded to the semiconductor die and to the electrically conductive leads, respectively. At least one of the first and second end portions of the electrically conductive ribbon includes a tapered portion having a second width smaller than the first width of the body portion.

8.

发明公开
POWER MODULE AND METHOD FOR MANUFACTURING SAME 审中-公开

公开(公告)号：US20230369195A1

公开(公告)日：2023-11-16

申请号：US17948332

申请日：2022-09-20

Applicant: Hyundai Motor Company , Kia Corporation

Inventor： Hyeon Uk Kim , Hyun Koo Lee , Jun Hee Park

IPC: H01L23/498 , H01L23/00 , H01L21/48

CPC classification number: H01L23/49844 , H01L24/48 , H01L24/32 , H01L24/73 , H01L23/49833 , H01L23/49861 , H01L23/49811 , H01L24/40 , H01L21/4839 , H01L21/4825 , H01L2924/381 , H01L2224/73215 , H01L2224/73265 , H01L2224/32225 , H01L2224/48155 , H01L2224/73263 , H01L2224/73213 , H01L2224/40155

Abstract: Disclosed are a power module and a method for manufacturing the same. A power module according to an embodiment of the present disclosure includes: a first substrate; a second substrate disposed spaced apart from the first substrate and including at least one metal layer; at least one chip disposed between the first substrate and the second substrate and in electrical contact with the metal layer; and a third substrate configured to be disposed spaced apart from the first substrate and the second substrate, electrically connect the chip and at least one external input terminal, include one or more conductive patterns each of which is connected to one of the at least one lead frame, and be formed in a multi-layer structure such that the one or more conductive patterns are not short-circuited to each other.