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公开(公告)号：US11263377B1
公开(公告)日：2022-03-01
申请号：US17219174
申请日：2021-03-31
申请人： Xilinx, Inc.
IPC分类号： G06F30/333 , G06F30/3308 , G06F30/398 , G06F11/00 , G01R31/28 , H01L25/00 , H03K19/00 , G06F115/08 , G06F11/08
摘要： A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.
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公开(公告)号：US20170110407A1
公开(公告)日：2017-04-20
申请号：US14885757
申请日：2015-10-16
申请人： Xilinx, Inc.
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L25/18
CPC分类号： H01L23/5385 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L22/14 , H01L23/3114 , H01L23/538 , H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/03312 , H01L2224/0332 , H01L2224/0345 , H01L2224/03462 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/73204 , H01L2224/81191 , H01L2224/92 , H01L2224/94 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/1515 , H01L2924/152 , H01L2924/153 , H01L2924/15311 , H01L2224/03 , H01L2924/014 , H01L2924/00014 , H01L21/78 , H01L2221/68304 , H01L2224/81 , H01L21/56 , H01L21/304 , H01L2224/11 , H01L2221/68381 , H01L22/00 , H01L2224/1181
摘要： Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.
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3.发明授权公开(公告)号：US09500700B1
公开(公告)日：2016-11-22
申请号：US14081461
申请日：2013-11-15
申请人： Xilinx, Inc.
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/31716
摘要： An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.
摘要翻译： 描述了能够进行数据通信的集成电路。 集成电路包括输入/输出端口; 多个数据转换器电路; 以及耦合在所述输入/输出端口和所述多个数据转换器电路之间的可编程互连电路，所述可编程互连电路使得所述多个数据转换器电路能够连接到所述集成电路的输入/输出端口。 还描述了能够进行集成电路中的数据通信的方法。
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公开(公告)号：US11755804B2
公开(公告)日：2023-09-12
申请号：US17646184
申请日：2021-12-28
申请人： Xilinx, Inc.
IPC分类号： G06F30/333 , G06F30/367 , G06F30/396 , G06F30/398 , G06F30/20 , G06F11/267 , G06F11/27 , H01L25/00 , H03K19/17732 , H03K19/17764 , G06F115/08 , H01L21/66
CPC分类号： G06F30/333 , H03K19/17732 , H03K19/17764 , G06F11/267 , G06F11/27 , G06F30/20 , G06F30/367 , G06F30/396 , G06F30/398 , G06F2115/08 , H01L22/34 , H01L25/00
摘要： An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
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公开(公告)号：US20230205959A1
公开(公告)日：2023-06-29
申请号：US17646184
申请日：2021-12-28
申请人： Xilinx, Inc.
IPC分类号： G06F30/333
CPC分类号： G06F30/333 , G06F2115/08
摘要： An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.
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6.发明授权公开(公告)号：US10754759B1
公开(公告)日：2020-08-25
申请号：US15889001
申请日：2018-02-05
申请人： Xilinx, Inc.
发明人： Amitava Majumdar , Georgios Tzimpragos , Jason Villarreal , Kumar Deepak , Jayashree Rangarajan
摘要： An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.
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公开(公告)号：US09989572B1
公开(公告)日：2018-06-05
申请号：US14494400
申请日：2014-09-23
申请人： Xilinx, Inc.
CPC分类号： G01R31/021 , G01R1/067 , G01R31/28
摘要： A method and a probe device for testing an interposer prior to assembly are described herein. The method includes coupling a plurality of probe tips of a probe device to the plurality of signal interconnect paths of the interposer to be tested. A test signal is provided from the probe device to the plurality of signal interconnect paths of the interposer and a quality characteristic of signal interconnect paths of the interposer is detected based on behavior of the interposer in response to the test signal.
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公开(公告)号：US11860228B2
公开(公告)日：2024-01-02
申请号：US17742363
申请日：2022-05-11
申请人： XILINX, INC.
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/318555 , G01R31/31727 , G01R31/318572
摘要： An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.
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公开(公告)号：US11585854B1
公开(公告)日：2023-02-21
申请号：US16108596
申请日：2018-08-22
申请人： Xilinx, Inc.
发明人： Da Cheng , Nui Chong , Amitava Majumdar , Ping-Chin Yeh , Cheang-Whang Chang
IPC分类号： G01R31/319 , G01R31/3185 , G01R31/317 , G01R31/28 , H03K3/03 , G06F13/42 , H03L7/099 , H03K19/00 , G06F1/324 , G06F1/3206 , H03K19/17784 , G01R19/165 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3296
摘要： Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.
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公开(公告)号：US11290095B1
公开(公告)日：2022-03-29
申请号：US17330042
申请日：2021-05-25
申请人： Xilinx, Inc.
发明人： Niravkumar Patel , Amitava Majumdar
摘要： An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.
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