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公开(公告)号：US11482273B1
公开(公告)日：2022-10-25
申请号：US17095592
申请日：2020-11-11
申请人： XILINX, INC.
发明人： Xiaobao Wang
摘要： Examples herein relate to devices that include a strobe tree circuit for capturing data using a memory-sourced strobe. In an example, a device includes a data capture path including first and second flip-flops, and a strobe tree including a comparator and first and second multiplexers. The comparator is configured to output complementary signals on first and second output nodes. First and second selection input nodes of the first multiplexer are connected to the first and second output nodes of the comparator, respectively. First and second selection input nodes of the second multiplexer are connected to the second and first output nodes of the comparator, respectively. The read strobe tree is configured to provide first and second signals output from the first and second multiplexers to first and second nodes, respectively. Clock input nodes of the first and second flip-flops are connected to the first and second nodes, respectively.
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公开(公告)号：US10823780B1
公开(公告)日：2020-11-03
申请号：US16112433
申请日：2018-08-24
申请人： Xilinx, Inc.
发明人： Andrew Tabalujan , Xiaobao Wang , Gubo Huang
IPC分类号： G01R31/28 , G01R19/257 , H04B17/20 , H01L25/065
摘要： Examples herein describe techniques for testing a receiver interface on a die. In one embodiment, the die includes tester circuitry which includes a digital to analog convertor (DAC) which outputs an analog test signal to a selector circuit (e.g., a multiplexer) which forwards the analog test signal to a receiver. By varying the analog test signal, the tester circuitry can identify one or more trip points corresponding to the receiver. That is, by monitoring the output of the receiver, a testing application can determine when the output of the receiver switches states thereby indicating that the analog test signal at the input of the receiver corresponds to the trip point of the receiver. In this manner, internal circuitry (e.g., the tester circuitry) can be used to test a receiver interface that may otherwise be inaccessible.
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公开(公告)号：US10656202B1
公开(公告)日：2020-05-19
申请号：US16137888
申请日：2018-09-21
申请人： Xilinx, Inc.
发明人： Sing-Keng Tan , Xiaobao Wang , Andrew Tabalujan , Gubo Huang
IPC分类号： G01R31/317 , G01R31/3185
摘要： Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.
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公开(公告)号：US09628082B1
公开(公告)日：2017-04-18
申请号：US14321577
申请日：2014-07-01
申请人： Xilinx, Inc.
IPC分类号： H03K17/16 , H03K19/177 , H03K3/01
CPC分类号： H03K19/177 , H03K3/01 , H03K19/018585
摘要： An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.
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公开(公告)号：US11750185B2
公开(公告)日：2023-09-05
申请号：US17482336
申请日：2021-09-22
申请人： XILINX, INC.
CPC分类号： H03K5/1565 , G11C7/222 , H03K5/134 , H03K5/135
摘要： Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.
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公开(公告)号：US10756019B1
公开(公告)日：2020-08-25
申请号：US16201663
申请日：2018-11-27
申请人： Xilinx, Inc.
发明人： Shuxian Wu , Xiaobao Wang , Xuemei Xi
IPC分类号： H01L23/538 , H01L23/00 , H01L25/18 , H01L25/04
摘要： A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.
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公开(公告)号：US10530324B1
公开(公告)日：2020-01-07
申请号：US16107117
申请日：2018-08-21
申请人： Xilinx, Inc.
发明人： Gubo Huang , Xiaobao Wang , Andrew Tabalujan , Sing-Keng Tan
摘要： Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.
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8.发明授权公开(公告)号：US09500700B1
公开(公告)日：2016-11-22
申请号：US14081461
申请日：2013-11-15
申请人： Xilinx, Inc.
CPC分类号： G01R31/2851 , G01R31/31715 , G01R31/31716
摘要： An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.
摘要翻译： 描述了能够进行数据通信的集成电路。 集成电路包括输入/输出端口; 多个数据转换器电路; 以及耦合在所述输入/输出端口和所述多个数据转换器电路之间的可编程互连电路，所述可编程互连电路使得所述多个数据转换器电路能够连接到所述集成电路的输入/输出端口。 还描述了能够进行集成电路中的数据通信的方法。
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公开(公告)号：US10659215B1
公开(公告)日：2020-05-19
申请号：US16135653
申请日：2018-09-19
申请人： Xilinx, Inc.
摘要： Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.
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10.发明授权公开(公告)号：US10063232B1
公开(公告)日：2018-08-28
申请号：US15703767
申请日：2017-09-13
申请人： Xilinx, Inc.
发明人： Sing-Keng Tan , Xiaobao Wang
IPC分类号： H03K19/0185 , H03K19/003 , H04L25/02 , H03K19/00
CPC分类号： H03K19/00384 , H03K19/0005 , H03K19/0185 , H04L25/0278
摘要： A transmitter includes: a driver circuit having a pull-up circuit, and a pull-down circuit, coupled to an output pad; a digitally controlled impedance (DCI) calibration circuit having a first reference driver, a second reference driver, and a reference resistor, the DCI calibration circuit configured to: generate a value for a first code by calibrating a first impedance in the first reference driver against the reference resistor; generate a value for a second code by calibrating a second impedance in the second reference driver against the first impedance; and adjust the value of the first code to match the first impedance with the second impedance; and a pre-driver circuit configured to supply the first code and the second code to the driver circuit for adjusting output impedance of the pull-up circuit and the pull-down circuit.
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