公开(公告)号：US10063232B1

公开(公告)日：2018-08-28

申请号：US15703767

申请日：2017-09-13

申请人： Xilinx, Inc.

发明人： Sing-Keng Tan ,  Xiaobao Wang

IPC分类号： H03K19/0185 ,  H03K19/003 ,  H04L25/02 ,  H03K19/00

CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H03K19/0185 ,  H04L25/0278

摘要： A transmitter includes: a driver circuit having a pull-up circuit, and a pull-down circuit, coupled to an output pad; a digitally controlled impedance (DCI) calibration circuit having a first reference driver, a second reference driver, and a reference resistor, the DCI calibration circuit configured to: generate a value for a first code by calibrating a first impedance in the first reference driver against the reference resistor; generate a value for a second code by calibrating a second impedance in the second reference driver against the first impedance; and adjust the value of the first code to match the first impedance with the second impedance; and a pre-driver circuit configured to supply the first code and the second code to the driver circuit for adjusting output impedance of the pull-up circuit and the pull-down circuit.

公开(公告)号：US10656202B1

公开(公告)日：2020-05-19

申请号：US16137888

申请日：2018-09-21

申请人： Xilinx, Inc.

发明人： Sing-Keng Tan ,  Xiaobao Wang ,  Andrew Tabalujan ,  Gubo Huang

IPC分类号： G01R31/317 ,  G01R31/3185

摘要： Examples of the present disclosure provide example devices that include an integrated circuit that has debugging capability. In some examples, a device includes an integrated circuit die. The integrated circuit die includes an input/output (IO) base cell and a debug port. The IO base cell has an interface node and a feedback node. The interface node is configured to be coupled to memory, such as via an interposer, for communication therebetween. The IO base cell is configurable to selectively output to the feedback node a signal that is on the interface node. The debug port has an input node and an output node. The input node is electrically connected to the feedback node. The debug port is configurable to selectively output to the output node a signal that is on the input node. The output node is configured to be coupled to a pin exterior to the integrated circuit die.

公开(公告)号：US10530324B1

公开(公告)日：2020-01-07

申请号：US16107117

申请日：2018-08-21

申请人： Xilinx, Inc.

发明人： Gubo Huang ,  Xiaobao Wang ,  Andrew Tabalujan ,  Sing-Keng Tan

IPC分类号： H03H7/38 ,  G01R27/14 ,  H01L23/00 ,  H01L25/18 ,  G11C7/10 ,  G11C5/06

摘要： Examples herein describe a die that includes a testing system (e.g., testing circuitry) for measuring the actual resistance of on-die resistors. When testing the die, an I/O element (e.g., a solder bump) can be used to sweep a voltage across the on-die resistor. The testing system identifies when the voltage across the on-die resistor reaches a predefined reference voltage and measures the corresponding current. Using the measured current and the reference voltage, the testing system can identify the actual resistance of the on-die resistor. In one embodiment, the on-die resistor is tunable such if the on-die resistor has a divergent value, the die can adjust its resistance value to the desired value.

公开(公告)号：US09696747B1

公开(公告)日：2017-07-04

申请号：US15253566

申请日：2016-08-31

申请人： Xilinx, Inc.

发明人： Sing-Keng Tan ,  Wenyi Song

IPC分类号： G05F3/16 ,  H03K17/687

CPC分类号： G05F3/16

摘要： An example a voltage regulator includes: a bias circuit coupled to an output node; a first operational amplifier having a first input coupled to the output node, a second input coupled to a reference voltage node, and an output coupled to a first node; a second operational amplifier having a first input coupled to the output node, a second input coupled to the reference voltage node, and an output coupled to a second node; an output transistor coupled between the output node and a ground node, the output transistor including a gate; first, second, and third stacked transistor pairs each serially coupled between the output node and the ground node, each transistor of the first, second, and third stacked transistor pairs including a gate; and switch circuits configured to selectively couple: the gates of the first and second stacked transistor pairs to the second node; and the gate of the output transistor to the first node.