公开(公告)号：US09619601B1

公开(公告)日：2017-04-11

申请号：US14603259

申请日：2015-01-22

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Valeria Mihalache

IPC: G06F17/50 ,  G06F9/44

CPC classification number: G06F17/5045 ,  G06F8/30 ,  G06F8/35 ,  G06F17/5009 ,  G06F17/5022

Abstract: An example method of generating a control and data flow graph for hardware description language (HDL) code specifying a circuit design is described. The method includes traversing an abstract syntax tree (AST) representation of the HDL code having a plurality of modules on a module-by-module basis. The method further includes adding an execution unit to the control and data flow graph for each module having concurrent paths. Each execution unit includes nodes in the control and data flow graph. The nodes include a loopback sink that merges the concurrent paths and a loopback source that receives feedback from the loopback sink and propagates the feedback to the concurrent paths.

公开(公告)号：US10296673B1

公开(公告)日：2019-05-21

申请号：US14723188

申请日：2015-05-27

Applicant: Xilinx, Inc.

Inventor： Ishita Ghosh ,  Hem C. Neema ,  Jason Villarreal ,  Saikat Bandyopadhyay ,  Kumar Deepak

IPC: G06F17/50

Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

公开(公告)号：US10255400B1

公开(公告)日：2019-04-09

申请号：US15473883

申请日：2017-03-30

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Xiaoyong Liu ,  Kumar Deepak

IPC: G06F17/50

Abstract: Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.

公开(公告)号：US10235272B2

公开(公告)日：2019-03-19

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F17/50 ,  G06F11/277 ,  G06F9/44

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US20180253368A1

公开(公告)日：2018-09-06

申请号：US15451068

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Mahesh Sankroj ,  Nikhil A. Dhume ,  Kumar Deepak

IPC: G06F11/36 ,  G06F11/277

CPC classification number: G06F11/3636 ,  G06F11/277 ,  G06F11/3628 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F17/5027

Abstract: An approach for debugging a circuit implementation of a software specification includes translating a high-level language debugging command into a hardware debugging command that specifies the value(s) of a condition in the circuit implementation, and a storage element(s) at which the value(s) of the condition is stored. The hardware debugging command is transmitted to a debug controller circuit that generates a single clock pulse to the circuit implementation. The debug controller circuit reads a value(s) from the storage element(s) specified by the hardware debugging command and determines whether or not the value(s) satisfies the condition. The debug controller circuit generates another single clock pulse in response to the value(s) read from the storage element(s) not satisfying the condition. Generation of pulses of the clock signal is suspended and data indicative of a breakpoint is output in response to the value(s) read from the storage element(s) satisfying the condition.

公开(公告)号：US10120831B1

公开(公告)日：2018-11-06

申请号：US15367611

申请日：2016-12-02

Applicant: Xilinx, Inc.

Inventor： Mahesh Sankroj ,  Jason Villarreal

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/16 ,  G06F13/40

Abstract: A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.

公开(公告)号：US10067854B2

公开(公告)日：2018-09-04

申请号：US15334182

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Kumar Deepak

IPC: G06F9/44 ,  G06F11/36

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.

公开(公告)号：US11003818B1

公开(公告)日：2021-05-11

申请号：US16790578

申请日：2020-02-13

Applicant: Xilinx, Inc.

Inventor： Ashish Kumar Jain ,  Saikat Bandyopadhyay ,  Jason Villarreal

IPC: G06F30/00 ,  G06F30/33 ,  G06F9/30 ,  G06F30/3308 ,  G06F7/499

Abstract: A method includes parsing and compiling a software code that includes a constraint bitwise operation with a first operand associated with a first constraint range and a second operand associated with a second constraint range. A first and a second plurality of ranges that spans the first and second constraint range are generated. In some embodiments, each constrained range is converted into a binary format having an upper bit portion and a lower bit portion. The upper bit portion for the each range remains unchanged. A resultant range associated with the constraint bitwise operation is determined based on performing the constraint bitwise operation on the first and the second plurality of ranges.

公开(公告)号：US10754759B1

公开(公告)日：2020-08-25

申请号：US15889001

申请日：2018-02-05

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Georgios Tzimpragos ,  Jason Villarreal ,  Kumar Deepak ,  Jayashree Rangarajan

IPC: G06F11/00 ,  G06F11/36

Abstract: An execution circuit inputs a plurality of data units, performs unit operations on the data units, and registers results of the unit operations in response to oscillations of a clock signal. A control circuit controls activation of the unit operations, and outputs a start signal to the execution circuit to activate each unit operation and/or a completion signal to indicate completion of each unit operation. A debug circuit stores breakpoint flags associated with the unit operations. Each breakpoint flag has a state that specifies whether to stop oscillations of the clock signal. The debug circuit further receives the start and/or completion signal and evaluates, while the clock signal oscillates to the execution circuit, a state of the start and/or completion signal and a state of the breakpoint flag associated with the unit operation. Oscillations of the clock signal are stopped in response to the evaluation of the signals.

公开(公告)号：US20180113787A1

公开(公告)日：2018-04-26

申请号：US15334182

申请日：2016-10-25

Applicant: Xilinx, Inc.

Inventor： Jason Villarreal ,  Kumar Deepak

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3632 ,  G06F11/3648

Abstract: Approaches for debugging include receiving by a hardware debug server, a high-level language (HLL) debugging command for setting a breakpoint in an HLL software specification. The hardware debug server translates the HLL debugging command into a hardware debugging command that specifies a condition of a hardware finite state machine that is representation of the software specification. The hardware debugging command is input to a simulator. The simulator adds a conditional breakpoint on the finite state machine in response to the hardware debugging command and executes a simulation of the finite state machine representation. Execution of the simulation is suspended in response to the detecting the condition in the finite state machine.