公开(公告)号：US20240330562A1

公开(公告)日：2024-10-03

申请号：US18192195

申请日：2023-03-29

申请人： Synopsys, Inc.

发明人： Piyush Verma ,  Joseph Robb Walston ,  Robert Lawrence Walker ,  Pranay Prakash ,  Jagat Patel ,  Mark Thomas Williams ,  Navneedh Shivakumar Maudgalya ,  Benoit Claudel

IPC分类号： G06F30/396 ,  G06F30/373

CPC分类号： G06F30/396 ,  G06F30/373

摘要： A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.

公开(公告)号：US12045553B2

公开(公告)日：2024-07-23

申请号：US17438795

申请日：2020-03-13

申请人： XENERGIC AB

发明人： Hemanth Prabhu ,  Babak Mohammadi

IPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396 ,  G11C7/12

CPC分类号： G06F30/392 ,  G06F30/394 ,  G06F30/396 ,  G11C7/12

摘要： A computer-implemented method for implementing integrated circuit with at least one RAM includes: defining memory portions of the RAM and obtaining memory portions; for each memory portion, generating a memory cell array block corresponding to the sizes of the memory portions, instances of the memory cell array blocks are inferred into a description of the integrated circuit in a hardware description language; for each block, generating timing and physical models; synthesizing description of circuit in the language, including peripheral logic for the blocks, to schematic representation of circuit elements; placing circuit elements, including blocks and peripheral logic, on circuit and routing wires between circuit elements taking into account the timing and physical models of blocks. An integrated circuit has memory portions of RAM, each having memory cell array block without, or partly without, peripheral logic; logic for each block implemented as standard cells, blocks and the logic distributed over circuit.

公开(公告)号：US11907007B2

公开(公告)日：2024-02-20

申请号：US17140399

申请日：2021-01-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Sheng-Hsiung Chen ,  Jack Liu ,  Yung-Chen Chien ,  Wei-Hsiang Ma ,  Chung-Hsing Wang

IPC分类号： G06F1/10 ,  G06F30/396

CPC分类号： G06F1/10 ,  G06F30/396

摘要： A clock distribution system includes a clock mesh structure which has a plurality of first metal patterns extending along a first axis, a plurality of second metal patterns extending along a second axis, a plurality of third metal patterns extending along a third axis. The plurality of first metal patterns, the plurality of second metal patterns, and the plurality of third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis.

公开(公告)号：US20230359797A1

公开(公告)日：2023-11-09

申请号：US18224337

申请日：2023-07-20

申请人： Samsung Electronics Co., Ltd.

发明人： Giyoung Yang ,  Ingyum Kim

IPC分类号： G06F30/392 ,  G06F30/396 ,  H01L27/088

CPC分类号： G06F30/392 ,  G06F30/396 ,  H01L27/0886

摘要： A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

公开(公告)号：US20230325573A1

公开(公告)日：2023-10-12

申请号：US18327025

申请日：2023-05-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： SHIH-YAO LIN ,  YI-LIN CHUANG ,  YIN-AN CHEN ,  SHIH FENG HONG

IPC分类号： G06F30/392 ,  G06F30/398 ,  G06F30/3953 ,  G06N20/10 ,  G06F30/27 ,  G06N3/08 ,  G06F30/396

CPC分类号： G06F30/392 ,  G06F30/398 ,  G06F30/3953 ,  G06N20/10 ,  G06F30/27 ,  G06N3/08 ,  G06F30/396

摘要： A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.

公开(公告)号：US11755097B2

公开(公告)日：2023-09-12

申请号：US17849707

申请日：2022-06-27

申请人： Baum Design Systems Co., Ltd.

发明人： In Hak Han ,  Jin Hyeong Park

IPC分类号： G06F30/396 ,  G06F119/06 ,  G06F1/3237 ,  G06F30/327

CPC分类号： G06F1/3237 ,  G06F30/327 ,  G06F30/396 ,  G06F2119/06

摘要： Example embodiments relate to a method for modeling power consumption of an integrated circuit, the method may comprise, determining, by the processor, a hierarchy structure regarding a gating level according to a clock flow of a plurality of clock gating cells included in the integrated circuit, determining, by the processor, a first clock gating domain corresponding to a first clock gating cell and a second clock gating domain corresponding to a second clock gating cell located in a lower level of the hierarchy of the first clock gating cell based on the hierarchy structure, calculating, by the processor, power consumption of the second clock gating domain based on a first logic level of a first clock gating enable signal applied to the first clock gating cell, and modeling, by the processor, power consumption of the integrated circuit based on the power consumption of the second clock gating domain.

公开(公告)号：US11741285B2

公开(公告)日：2023-08-29

申请号：US17361854

申请日：2021-06-29

申请人： Samsung Electronics Co., Ltd.

发明人： Giyoung Yang ,  Ingyum Kim

IPC分类号： G06F30/392 ,  G06F30/396 ,  H01L27/088

CPC分类号： G06F30/392 ,  G06F30/396 ,  H01L27/0886

摘要： A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

公开(公告)号：US11599700B2

公开(公告)日：2023-03-07

申请号：US17247085

申请日：2020-11-30

申请人： The Regents of the University of California

发明人： Rafael Possignolo ,  Jose Renau

IPC分类号： G06F30/327 ,  G06F30/331 ,  G06F30/392 ,  G06F30/398 ,  G06F30/396

摘要： Techniques include retrieving a first structural netlist (SN1) that indicates electronic components, values of programmable parameters, and connections for a first electronic circuit, and retrieving a first placed and routed netlist (PR1) that indicates physical placement of the electronic components and physical routing of connections for SN1. Also retrieved is a second structural netlist (SN2) for a different second electronic circuit. For each component in SN2, a matching component, if any, is found in SN1 based on type of component and inputs that are output from other matching components. A different second placed and routed netlist (PR2) is generated for the second circuit by deriving new placement and routing for only for non-matching components in SN2.

公开(公告)号：US20230036554A1

公开(公告)日：2023-02-02

申请号：US17963080

申请日：2022-10-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chieh TSAI ,  Shao-Yu WANG

IPC分类号： G06F30/396 ,  G06F1/10 ,  G06F30/392

摘要： A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

公开(公告)号：US11526641B2

公开(公告)日：2022-12-13

申请号：US17411695

申请日：2021-08-25

申请人： Synopsys, Inc.

发明人： Lisa McIlwain ,  Fahim Rahim ,  Guillaume Plassan ,  Dipti Ranjan Senapati

IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/337 ,  G06F30/396 ,  G06F30/398 ,  G06F117/04

摘要： Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.