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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10134838B2

    公开(公告)日：2018-11-20

    申请号：US15820053

    申请日：2017-11-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myoung-Ho Kang ,  Jung-Ho Do ,  Giyoung Yang ,  Seungyoung Lee

    IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/78

    Abstract: A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

    FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME
    3.
    发明公开
    FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240061039A1

    公开(公告)日：2024-02-22

    申请号：US18194643

    申请日：2023-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

    IPC: G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/318525 ,  G01R31/318541 ,  G01R31/31725

    Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220058327A1

    公开(公告)日：2022-02-24

    申请号：US17361854

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Giyoung Yang ,  Ingyum Kim

    IPC: G06F30/392 ,  H01L27/088 ,  G06F30/396

    Abstract: A semiconductor device includes a substrate having an active region, first standard cells arranged in a first row on the active region, second standard cells arranged in a second row on the active region and having a first boundary with the first standard cells, a third standard cells arranged in a third row on the active region and having a second boundary with the first standard cells, and a plurality of power supply lines, respectively arranged along boundaries. Each of the first to third standard cells includes a plurality of fin patterns extending in the first direction, and the plurality of fin patterns are arranged in a second direction, so as not to be disposed on at least one boundary, among the first and second boundaries.

    Flip-flops and scan chain circuits including the same
    5.
    发明授权
    Flip-flops and scan chain circuits including the same 有权

    公开(公告)号：US12044733B2

    公开(公告)日：2024-07-23

    申请号：US18194643

    申请日：2023-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

    IPC: G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/318525 ,  G01R31/31725 ,  G01R31/318541

    Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

    Integrated circuit including standard cell and filler cell
    7.
    发明授权
    Integrated circuit including standard cell and filler cell 有权

    公开(公告)号：US12230625B2

    公开(公告)日：2025-02-18

    申请号：US18591089

    申请日：2024-02-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hakchul Jung ,  Ingyum Kim ,  Giyoung Yang ,  Jaewoo Seo

    IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

    Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

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