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公开(公告)号:US11948932B2
公开(公告)日:2024-04-02
申请号:US17528242
申请日:2021-11-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hakchul Jung , Ingyum Kim , Giyoung Yang , Jaewoo Seo
IPC: H01L27/02 , H01L29/06 , H01L29/423 , H01L29/786
CPC classification number: H01L27/0207 , H01L29/0665 , H01L29/42392 , H01L29/78696
Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.
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公开(公告)号:US20220245515A1
公开(公告)日:2022-08-04
申请号:US17582715
申请日:2022-01-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hayoon YI , Jaewoo Seo
Abstract: According to various embodiments, an electronic device may be provided, the electronic device comprising a memory and at least one processor, wherein the at least one processor is configured to by applying a noise value to weight values of at least a part of a plurality of layers included in an artificial intelligence model stored in the electronic device, obtain the weight values to which the noise value is applied, when an event for executing the artificial intelligence model is identified, obtain, based on computation of data input to the at least a part of the plurality of layers, computation data by using the weight values to which the noise value is applied, and obtain output data, based on the obtained computation data and the applied noise value.
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公开(公告)号:US12034008B2
公开(公告)日:2024-07-09
申请号:US18336754
申请日:2023-06-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sanghoon Baek , Jungho Do , Jaewoo Seo , Jisu Yu
IPC: H01L27/02 , H01L23/48 , H01L27/118
CPC classification number: H01L27/11807 , H01L23/481 , H01L27/0207 , H01L2027/11829 , H01L2027/11864 , H01L2027/11881
Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.
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公开(公告)号:US11755809B2
公开(公告)日:2023-09-12
申请号:US17458948
申请日:2021-08-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jisu Yu , Jaewoo Seo , Hyeongyu You , Sanghoon Baek , Jonghoon Jung
IPC: G06F30/00 , G06F30/392 , H01L23/50 , H01L27/02
CPC classification number: G06F30/392 , H01L23/50 , H01L27/0207
Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.
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公开(公告)号:US11645387B2
公开(公告)日:2023-05-09
申请号:US16965950
申请日:2019-01-29
Inventor: Jaewoo Seo , Suin Kang , Mincheol Kim , Hyemin Kim , Huykang Kim , Kiseok Do , Jooyeon Moon , Hyunmin Song , Sejoon Oh , Sooyeon Lee
CPC classification number: G06F21/561 , G06F8/53 , G06F18/22 , G06F21/563 , G06V10/761 , G06F2221/033
Abstract: An electronic device is disclosed. An electronic device according to various embodiments comprises: a processor; and a memory electrically connected to the processor, wherein the processor may be configured to: obtain a plurality of first parameters associated with attributes of at least one malicious code and a plurality of second parameters associated with a system in which the at least one malicious code is executed; obtain a similarity on the basis of a first comparison result according to a first comparison method between the plurality of first parameters and a second comparison result according to a second comparison method between the plurality of second parameters; and classify the at least one malicious code into at least one cluster on the basis of the similarity between the at least one malicious code. Other various embodiments may be provided.
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公开(公告)号:US12230625B2
公开(公告)日:2025-02-18
申请号:US18591089
申请日:2024-02-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hakchul Jung , Ingyum Kim , Giyoung Yang , Jaewoo Seo
IPC: H01L27/02 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.
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公开(公告)号:US12147751B2
公开(公告)日:2024-11-19
申请号:US17360355
申请日:2021-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungman Lim , Hakchul Jung , Sanghoon Baek , Jaewoo Seo , Jisu Yu , Hyeongyu You
IPC: G06F30/3953 , G06F30/327 , G06F119/06 , H01L23/528
Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.
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公开(公告)号:US20220262786A1
公开(公告)日:2022-08-18
申请号:US17670626
申请日:2022-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jisu Yu , Jungho Do , Jaewoo Seo , Hyeongyu You , Minjae Jeong
IPC: H01L27/02 , H01L27/118
Abstract: An integrated circuit including a first standard cell placed continuously on a row having a first height and a row having a second height different from the first height. The integrated circuit also includes a second standard cell continuously placed on a row having the first height and a row having the second height, a plurality of first power lines formed on boundaries of the plurality of rows and configured to supply a first supply voltage to the standard cells, and a plurality of second power lines formed on boundaries of the plurality of rows and configured to supply a second supply voltage to the standard cells. A placement sequence of the power lines supplying a voltage to the first standard cell being different from a placement sequence of the power lines supplying a voltage to the second standard cell.
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公开(公告)号:US20220253283A1
公开(公告)日:2022-08-11
申请号:US17563836
申请日:2021-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jaewoo Seo , Minjae Jeong , Yongdurk Kim , Giyoung Yang , Eungchul Jun , Changbeom Kim , Moogyu Bae
IPC: G06F7/505 , H03K17/687 , H01L27/02 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row
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公开(公告)号:US20240203973A1
公开(公告)日:2024-06-20
申请号:US18591089
申请日:2024-02-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hakchul Jung , Ingyum Kim , Giyoung Yang , Jaewoo Seo
IPC: H01L27/02 , H01L29/06 , H01L29/423 , H01L29/786
CPC classification number: H01L27/0207 , H01L29/0665 , H01L29/42392 , H01L29/78696
Abstract: An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.
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