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    INTEGRATED CIRCUIT INCLUDING CELLS OF DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT
    2.
    发明申请
    INTEGRATED CIRCUIT INCLUDING CELLS OF DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220058326A1

    公开(公告)日：2022-02-24

    申请号：US17183630

    申请日：2021-02-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonghyun Lee ,  Jungho Do

    IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528

    Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200220548A1

    公开(公告)日：2020-07-09

    申请号：US16820835

    申请日：2020-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong SONG ,  Jungho Do ,  Seungyoung Lee ,  Jonghoon Jung

    IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12131999B2

    公开(公告)日：2024-10-29

    申请号：US18512527

    申请日：2023-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

    SEMICONDUCTOR DEVICES
    7.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220328408A1

    公开(公告)日：2022-10-13

    申请号：US17532052

    申请日：2021-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11101803B2

    公开(公告)日：2021-08-24

    申请号：US16820835

    申请日：2020-03-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taejoong Song ,  Jungho Do ,  Seungyoung Lee ,  Jonghoon Jung

    IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

    Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

    CELL ARCHITECTURE BASED ON MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR
    9.
    发明申请
    CELL ARCHITECTURE BASED ON MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR 审中-公开

    公开(公告)号：US20190386103A1

    公开(公告)日：2019-12-19

    申请号：US16257890

    申请日：2019-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L27/092 ,  H01L23/522

    Abstract: A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.

    SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20240395713A1

    公开(公告)日：2024-11-28

    申请号：US18582859

    申请日：2024-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangcheol Na ,  Jungho Do ,  Kyoungwoo Lee ,  Gukhee Kim ,  Minchan Gwak

    IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device includes first power lines extending on a substrate in a first direction and spaced apart from each other in a second direction, back side power structures on a lower surface of the substrate, standard cells each including an active pattern, a gate pattern intersecting the active pattern, and contacts, power tap cells between at least some of the standard cells and each including vertical power vias, and second power lines electrically connecting at least some of the first power lines to each other. A first portion of the second power lines may extend onto the power tap cells and a second portion of the second power lines that is different from the first portion may extend onto the standard cells. The power tap cells may be arranged in every three or more rows of the standard cells in the second direction in a zigzag pattern.

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