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    ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
    1.
    发明公开
    ASYMMETRIC NAND GATE CIRCUIT, CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME 失效

    公开(公告)号：US20240235533A9

    公开(公告)日：2024-07-11

    申请号：US18373017

    申请日：2023-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounggon Kang ,  Dalhee Lee

    IPC: H03K3/037 ,  G06F1/08 ,  H03K19/20

    CPC classification number: H03K3/037 ,  G06F1/08 ,  H03K19/20 ,  H03K3/012

    Abstract: A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

    Flip-flop circuit including control signal generation circuit
    2.
    发明授权
    Flip-flop circuit including control signal generation circuit 有权

    公开(公告)号：US11863188B2

    公开(公告)日：2024-01-02

    申请号：US17843585

    申请日：2022-06-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounggon Kang ,  Dalhee Lee

    IPC: H03K3/03 ,  H03K3/037 ,  H03K19/20

    CPC classification number: H03K3/0372 ,  H03K19/20

    Abstract: A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.

    Clock gating cell with low power and integrated circuit including the same
    3.
    发明授权
    Clock gating cell with low power and integrated circuit including the same 有权

    公开(公告)号：US11336269B2

    公开(公告)日：2022-05-17

    申请号：US16886187

    申请日：2020-05-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dalhee Lee ,  Byounggon Kang

    IPC: H03K3/037 ,  H03K19/20 ,  G06F1/04

    Abstract: An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.

    FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME
    4.
    发明公开
    FLIP-FLOPS AND SCAN CHAIN CIRCUITS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240061039A1

    公开(公告)日：2024-02-22

    申请号：US18194643

    申请日：2023-04-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

    IPC: G01R31/3185 ,  G01R31/317

    CPC classification number: G01R31/318525 ,  G01R31/318541 ,  G01R31/31725

    Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11424251B2

    公开(公告)日：2022-08-23

    申请号：US17219175

    申请日：2021-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounggon Kang ,  Taejun Yoo ,  Seunghyun Yang ,  Dalhee Lee

    IPC: H01L27/11 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528

    Abstract: A semiconductor device is provided. The semiconductor device includes power supply lines extending in a first direction; first transistors, each of which is formed in a first region and has a first threshold voltage; and second transistors, each of which is formed in a second region and has a second threshold voltage higher than the first threshold voltage. One of the plurality of power supply lines is interposed between the first region and the second region, the first transistors implement a first portion of a multiplexer, a clock buffer and a first latch that are disposed on a data path, the second transistors implement a second portion of the multiplexer circuit and a second latch that are disposed on a feedback path, and the first portion of the multiplexer circuit and the second portion of the multiplexer circuit are disposed in a common location along the first direction.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11362032B2

    公开(公告)日：2022-06-14

    申请号：US16919670

    申请日：2020-07-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Changbeom Kim ,  Dalhee Lee ,  Eun-Hee Choi

    IPC: H01L21/00 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L27/092 ,  H01L27/02 ,  H01L27/118 ,  H01L29/423

    Abstract: A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

    Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same
    8.
    发明授权
    Asymmetric NAND gate circuit, clock gating cell and integrated circuit including the same 有权

    公开(公告)号：US12249993B2

    公开(公告)日：2025-03-11

    申请号：US18373017

    申请日：2023-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byounggon Kang ,  Dalhee Lee

    IPC: H03K3/037 ,  G06F1/08 ,  H03K3/012 ,  H03K19/20

    Abstract: A clock gating cell is provided. The clock gating cell includes: an inverter circuit configured to generate an inverted clock signal by inverting a clock signal; a first control circuit configured to receive the inverted clock signal, an enable signal, and a scan enable signal, and output a first internal signal at a first node; a second control circuit configured to receive the first internal signal, the clock signal, the enable signal, and the scan enable signal, and output a second internal signal at a second node; and an output driver configured to receive the second internal signal, and output an output clock signal to an output node and a third internal signal to a third node. The first control circuit and the second control circuit are configured to receive the third internal signal at the third node.

    LOW POWER FLIP-FLOP
    9.
    发明公开
    LOW POWER FLIP-FLOP 审中-公开

    公开(公告)号：US20240128952A1

    公开(公告)日：2024-04-18

    申请号：US18377777

    申请日：2023-10-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Dalhee Lee

    IPC: H03K3/012 ,  G01R31/3185 ,  H03K3/037 ,  H03K19/20

    CPC classification number: H03K3/012 ,  G01R31/318541 ,  H03K3/0372 ,  H03K19/20

    Abstract: A low power flip-flop includes a master section including a multiplexer, a first AND-OR-Inverter (AOI) gate circuit, a second AOI gate circuit, and a first inverter circuit and configured to receive a data input signal, a scan input signal, a scan enable signal, and an inverted scan enable signal, and output a second internal signal and a third internal signal, a slave section including a third AOI gate circuit, a fourth AOI gate circuit, and a second inverter circuit, and configured to receive the second and third internal signals to output an output signal, and a third inverter circuit configured to generate the inverted scan enable signal. The first to fourth AOI gate circuits are configured to receive a clock signal.

    High-speed flip flop circuit including delay circuit
    10.
    发明授权
    High-speed flip flop circuit including delay circuit 有权

    公开(公告)号：US11509295B2

    公开(公告)日：2022-11-22

    申请号：US17340215

    申请日：2021-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byounggon Kang ,  Changbeom Kim ,  Dalhee Lee ,  Wookyu Kim

    IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/3562

    Abstract: A flip flop includes a master latch and a slave latch. The master latch includes a delay circuit configured to receive a clock signal and generate a first internal signal, and is configured to generate an internal output signal by latching a data signal based on the first internal signal. The slave latch is configured to generate a final signal by latching the internal output signal. The delay circuit is further configured to generate the first internal signal by delaying the clock signal by a delay time when the clock signal has a first logic level and generate the first internal signal based on the data signal when the clock signal has a second logic level.

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