公开(公告)号：US20240061039A1

公开(公告)日：2024-02-22

申请号：US18194643

申请日：2023-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318525 ,  G01R31/318541 ,  G01R31/31725

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.

公开(公告)号：US12044733B2

公开(公告)日：2024-07-23

申请号：US18194643

申请日：2023-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounggon Kang ,  Dalhee Lee ,  Giyoung Yang ,  Minji Kim ,  Taejung Seol ,  Jaebeom Yang

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318525 ,  G01R31/31725 ,  G01R31/318541

Abstract: A flip-flop circuit may include a selection circuit, a master latch circuit and a slave latch circuit. The selection circuit includes a multiplexer and first and second inverters. The multiplexer outputs a data signal or a scan input signal to a first node in response to an enable signal. The first inverter is connected to the first node and provides an inversion of a signal of the first node to a second node in response to a clock signal. The second inverter is connected to the second node and provides an inversion of the signal of the second node to a third node in response to the clock signal and a signal of a fourth node. The master latch circuit is connected between the third and fourth nodes. The slave latch circuit is connected between the fourth node and an output terminal of the flip-flop circuit.