公开(公告)号：US11526641B2

公开(公告)日：2022-12-13

申请号：US17411695

申请日：2021-08-25

申请人： Synopsys, Inc.

发明人： Lisa McIlwain ,  Fahim Rahim ,  Guillaume Plassan ,  Dipti Ranjan Senapati

IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/3312 ,  G06F30/337 ,  G06F30/396 ,  G06F30/398 ,  G06F117/04

摘要： Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.