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公开(公告)号：US09812340B2
公开(公告)日：2017-11-07
申请号：US15074110
申请日：2016-03-18
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu , Fu-Tang Huang
IPC: H01L21/00 , H01L21/56 , H01L23/00 , H01L21/683 , H01L21/768 , H01L23/31
CPC classification number: H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05567 , H01L2224/12105 , H01L2224/131 , H01L2224/24153 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
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公开(公告)号：US09324585B2
公开(公告)日：2016-04-26
申请号：US13654754
申请日：2012-10-18
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu , Fu-Tang Huang
CPC classification number: H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05567 , H01L2224/12105 , H01L2224/131 , H01L2224/24153 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。
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公开(公告)号：US20140183721A1
公开(公告)日：2014-07-03
申请号：US13846579
申请日：2013-03-18
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Yan-Heng Chen , Chiang-Cheng Chang , Jung-Pang Huang , Hsi-Chang Hsu , Yan-Yi Liao
CPC classification number: H01L21/561 , H01L21/568 , H01L23/3114 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L2224/12105
Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.
Abstract translation: 提供一种半导体封装的制造方法，其包括以下步骤：提供具有粘合层和至少具有保护层的半导体元件的载体; 通过保护层将半导体元件设置在载体的粘合剂层上; 在用于封装半导体元件的载体的粘合剂层上形成密封剂; 去除载体和粘合剂层以将保护层暴露于密封剂; 以及去除所述保护层以使所述半导体元件暴露于所述密封剂。 由于半导体元件被保护层保护以防止在去除粘合剂层的过程中损坏，所以产品产率提高。
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公开(公告)号：US20140154842A1
公开(公告)日：2014-06-05
申请号：US14174988
申请日：2014-02-07
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu
IPC: H01L21/56 , H01L21/78 , H01L21/673 , H01L21/768
CPC classification number: H01L21/56 , H01L21/4832 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/673 , H01L21/67333 , H01L21/67763 , H01L21/68 , H01L21/683 , H01L21/76877 , H01L21/78 , H01L23/31 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/96 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2224/97 , H01L2924/1815 , H01L2224/11 , H01L2224/03 , H01L2924/014
Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
Abstract translation: 半导体封装的制造方法包括以下步骤：提供在其表面上形成有凹部和释放层的载体; 在凹部中的脱模层上设置芯片; 在芯片和释放层上形成密封剂; 去除释放层和载体; 并在密封剂和芯片上形成电路结构。 凹部的设计有助于芯片对准以防止其移位，从而提高产品的可靠性。 还提供了通过制造方法制造的半导体封装。
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公开(公告)号：US20130341774A1
公开(公告)日：2013-12-26
申请号：US13628795
申请日：2012-09-27
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Shih-Kuang Chiu
IPC: H01L23/495 , H01L21/56
CPC classification number: H01L24/19 , H01L21/561 , H01L21/563 , H01L21/568 , H01L23/3128 , H01L23/5389 , H01L24/96 , H01L2224/12105 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
Abstract: A semiconductor package is provided, including: an insulating layer; a semiconductor element embedded in the insulating layer; an adhesive body embedded in the insulating layer, wherein a portion of the semiconductor element is embedded in the adhesive body; a patterned metal layer embedded in the adhesive body and electrically connected to the semiconductor element; and a redistribution structure formed on the insulating layer and electrically connected to the patterned metal layer. By embedding the semiconductor element in the adhesive body, the present invention can securely fix the semiconductor element at a predetermined position without any positional deviation, thereby improving the product yield.
Abstract translation: 提供一种半导体封装，包括：绝缘层; 嵌入绝缘层中的半导体元件; 嵌入在所述绝缘层中的粘合体，其中所述半导体元件的一部分嵌入所述粘合体中; 图案化金属层，其嵌入在所述粘合体中并电连接到所述半导体元件; 以及形成在绝缘层上并与图案化的金属层电连接的再分布结构。 通过将半导体元件嵌入到粘合体中，本发明可以将半导体元件可靠地固定在预定位置而没有任何位置偏差，从而提高产品产量。
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Patent Agency Ranking
公开(公告)号：US08766456B2
公开(公告)日：2014-07-01
申请号：US13660223
申请日：2012-10-25
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Hsi-Chang Hsu , Hsin-Hung Chou , Hung-Wen Liu , Hsin-Yi Liao , Chiang-Cheng Chang
CPC classification number: H01L23/49816 , H01L21/568 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/73267 , H01L2224/82005 , H01L2225/1035 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/00
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.
Abstract translation: 提供一种制造半导体封装的方法，包括：将半导体元件设置在载体上; 在所述载体上形成密封剂以密封所述半导体元件; 形成穿透所述密封剂的至少一个通孔; 在通孔中形成中空的导电通孔，同时在半导体元件的有源表面和密封剂上形成电路层; 在电路层上形成绝缘层; 并移除载体。 通过同时形成导电通孔和电路层，本发明消除了在形成电路层之前形成电介质层并省去常规化学机械抛光（CMP）工艺的需要，从而大大提高了制造效率。
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公开(公告)号：US20140134797A1
公开(公告)日：2014-05-15
申请号：US14013512
申请日：2013-08-29
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chieh-Yuan Chi , Jung-Pang Huang , Yan-Heng Chen , Hsi-Chang Hsu , Chiang-Cheng Chang , Shih-Kuang Chiu
IPC: H01L21/56
CPC classification number: H01L21/561 , H01L21/568 , H01L23/3121 , H01L24/96 , H01L2924/12042 , H01L2924/00
Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.
Abstract translation: 公开了一种制造半导体封装件的方法，其包括以下步骤：提供具有释放层和依次在其上形成的粘合剂层的载体; 在所述粘合剂层上设置多个半导体芯片; 在粘合剂层上形成密封剂以封装半导体芯片; 将衬底设置在密封剂上; 将释放层暴露于通过载体的光，以便去除释放层和载体; 然后去除粘合剂层，从而有效地防止半导体芯片暴露于光，以避免对半导体芯片的任何光损坏。
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公开(公告)号：US10049955B2
公开(公告)日：2018-08-14
申请号：US15497964
申请日：2017-04-26
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu
Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
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公开(公告)号：US20160196990A1
公开(公告)日：2016-07-07
申请号：US15074110
申请日：2016-03-18
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu , Fu-Tang Huang
IPC: H01L21/56 , H01L21/768 , H01L21/683
CPC classification number: H01L21/568 , H01L21/561 , H01L21/6835 , H01L21/76802 , H01L21/76834 , H01L21/76877 , H01L23/3128 , H01L24/19 , H01L24/96 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/05567 , H01L2224/12105 , H01L2224/131 , H01L2224/24153 , H01L2924/00014 , H01L2924/014 , H01L2224/05552
Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
Abstract translation: 提供一种制造半导体封装的方法，包括：通过粘合剂层将多个半导体元件设置在载体上，使载体的一部分从粘合剂层露出; 形成密封剂以封装半导体元件; 去除粘合剂层和载体以暴露半导体元件; 以及在半导体元件上形成积聚结构。 由于当温度变化时粘合剂层被分成多个不会由于膨胀或收缩而相互影响的分离部分，所以本发明防止了半导体元件在成型过程中的位置偏差，从而提高了对准精度。
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公开(公告)号：US09899237B2
公开(公告)日：2018-02-20
申请号：US14174988
申请日：2014-02-07
Applicant: Siliconware Precision Industries Co., Ltd
Inventor： Chiang-Cheng Chang , Meng-Tsung Lee , Jung-Pang Huang , Shih-Kuang Chiu
IPC: H01L23/00 , H01L23/31 , H01L21/56 , H01L21/673 , H01L21/768 , H01L21/78 , H01L21/68 , H01L21/48 , H01L21/683 , H01L21/677
CPC classification number: H01L21/56 , H01L21/4832 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/673 , H01L21/67333 , H01L21/67763 , H01L21/68 , H01L21/683 , H01L21/76877 , H01L21/78 , H01L23/31 , H01L23/3107 , H01L23/3114 , H01L23/3121 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/96 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2224/97 , H01L2924/1815 , H01L2224/11 , H01L2224/03 , H01L2924/014
Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
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