公开(公告)号：US11527491B2

公开(公告)日：2022-12-13

申请号：US17337770

申请日：2021-06-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chun-Tang Lin ,  Shou-Qi Chang ,  Yu-Hsiang Hsieh

IPC: H01L23/00 ,  H01L23/14 ,  H01L25/065 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31

Abstract: A substrate structure has an obtuse portion formed between a side surface and a bottom surface of a substrate body. The obtuse portion includes a plurality of turning surfaces to disperse the stress of the substrate body generated in the packaging process. Therefore, the substrate body is prevented from being cracked. A method for fabricating the substrate structure and an electronic package including the substrate structure are also provided.

公开(公告)号：US20170148761A1

公开(公告)日：2017-05-25

申请号：US15400608

申请日：2017-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

公开(公告)号：US20160126126A1

公开(公告)日：2016-05-05

申请号：US14836613

申请日：2015-08-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi

IPC: H01L21/683 ,  H01L21/768 ,  H01L21/027 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L23/295 ,  H01L24/19 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041

Abstract: A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles.

Abstract translation: 提供一种制造封装结构的方法，包括以下步骤：在载体上设置具有面向载体的有源表面的半导体芯片; 在载体上形成图案化的抗蚀剂层; 在载体上形成暴露半导体芯片的非活性表面和图案化抗蚀剂层的表面的密封剂; 并移除载体以获得包装结构。 此后，可以在封装结构的相对侧上形成再分布层，并且可以通过钻孔在图案化的抗蚀剂层中形成多个通孔，从而允许在通孔中形成用于电气的多个导电通孔 连接包装结构的相对侧上的再分布层。 因此，本发明克服了通过直接钻削具有填料颗粒的密封剂引起的通孔的表面粗糙度的常规缺陷。

公开(公告)号：US20150132893A1

公开(公告)日：2015-05-14

申请号：US14604128

申请日：2015-01-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。

公开(公告)号：US20150035163A1

公开(公告)日：2015-02-05

申请号：US14012402

申请日：2013-08-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将半导体元件放置在载体的凹槽中; 在所述半导体元件上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分以将所述载体的第二载体保持在所述凹槽的侧壁上，以使所述第二部分用作支撑部分。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。

公开(公告)号：US20140342506A1

公开(公告)日：2014-11-20

申请号：US14146171

申请日：2014-01-02

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Hung-Wen Liu

IPC: H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract translation: 本发明公开了一种制造半导体封装的方法，包括提供具有绝缘层和至少嵌入绝缘层中的半导体元件的封装单元，其中半导体元件从绝缘层露出，并且形成在多个凹部中 绝缘层; 并且将再分布结构电连接到半导体元件。 凹陷部分的形成释放绝缘层的应力并防止绝缘层发生翘曲。

公开(公告)号：US20140332976A1

公开(公告)日：2014-11-13

申请号：US14013420

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US20140264928A1

公开(公告)日：2014-09-18

申请号：US13922798

申请日：2013-06-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/52 ,  H01L21/56 ,  H01L23/28

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：在插入件上设置多个第一半导体元件; 在所述插入件上形成用于封装所述第一半导体元件的第一密封剂; 在所述第一半导体元件上设置多个第二半导体元件; 在所述第一半导体元件和所述第一密封剂上形成用于封装所述第二半导体元件的第二密封剂; 并使插入件变薄，从而减小整体堆叠厚度并防止插入件的翘曲。

公开(公告)号：US20140191386A1

公开(公告)日：2014-07-10

申请号：US13894716

申请日：2013-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Mei-Chin Lee ,  Wang-Ting Chen ,  Chi-Tung Yeh ,  Chun-Tang Lin ,  Yi-Che Lai

IPC: H01L21/48 ,  H01L23/373

CPC classification number: H01L23/3738 ,  H01L23/367 ,  H01L23/42 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer.

Abstract translation: 提供半导体封装。 半导体封装包括衬底; 半导体元件具有相反的有源和非活性表面，并经由其活性表面设置在衬底上，其中半导体元件的非活性表面被粗糙化; 接合到半导体元件的非活性表面的导热层; 以及布置在导热层上的散热器。 粗糙化的非活性表面促进了半导体元件和导热层之间的结合，从而消除了执行镀金工艺和使用焊剂的需要，从而减少导热层中空隙的形成。

公开(公告)号：US20140138791A1

公开(公告)日：2014-05-22

申请号：US13753930

申请日：2013-01-30

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chien-Feng Chan ,  Chun-Tang Lin ,  Yi Che Lai

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L24/94 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L28/00 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/19103 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor chip having opposite first and second surfaces; an RDL structure formed on the first surface of the semiconductor chip and having opposite third and fourth surfaces and a plurality of first conductive through holes penetrating the third and fourth surfaces thereof, wherein the RDL structure is formed on the semiconductor chip through the fourth surface thereof and electrically connected to the semiconductor chip through a plurality of first conductive elements, and the third surface of the RDL structure has a redistribution layer formed thereon; a plurality of conductive bumps formed on the redistribution layer; and an encapsulant formed on the first surface of the semiconductor chip for encapsulating the RDL structure, wherein the conductive bumps are embedded in and exposed from the encapsulant. The invention effectively prevents warpage of the semiconductor package and improves the electrical connection significantly.

Abstract translation: 提供半导体封装。 半导体封装包括具有相反的第一和第二表面的半导体芯片; 形成在半导体芯片的第一表面上并且具有相反的第三和第四表面的RDL结构以及穿过其第三和第四表面的多个第一导电通孔，其中RDL结构通过其第四表面形成在半导体芯片上 并通过多个第一导电元件与半导体芯片电连接，并且RDL结构的第三表面在其上形成再分布层; 形成在再分配层上的多个导电凸块; 以及密封剂，其形成在所述半导体芯片的用于封装所述RDL结构的所述第一表面上，其中所述导电凸块嵌入并暴露于所述密封剂。 本发明有效地防止了半导体封装的翘曲，并显着地改善了电连接。