公开(公告)号：US09899303B2

公开(公告)日：2018-02-20

申请号：US14862457

申请日：2015-09-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L23/49 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

公开(公告)号：US09607941B2

公开(公告)日：2017-03-28

申请号：US14669527

申请日：2015-03-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Mu-Hsuan Chan

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/532 ,  H01L23/522 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

公开(公告)号：US20160013146A1

公开(公告)日：2016-01-14

申请号：US14736436

申请日：2015-06-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Chun-Tang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/18162

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract translation: 提供了一种制造封装结构的方法，包括以下步骤：在第一载体上依次形成金属层和电介质层，其中电介质层具有暴露金属层部分的多个开口; 将电子元件经由其活性表面设置在电介质层上，并将金属球的多个导电元件安装在金属层的暴露部分上; 在所述电介质层上形成密封剂以封装所述电子元件和所述导电元件; 移除第一载体; 以及将所述金属层图案化成第一电路并在所述电介质层上形成第二电路，其中所述第二电路电连接到所述电子元件和所述第一电路。 本发明省去了常规的激光烧蚀工艺，以简化制造工艺，节省制造成本并提高产品的可靠性。

公开(公告)号：US20140134797A1

公开(公告)日：2014-05-15

申请号：US14013512

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Yuan Chi ,  Jung-Pang Huang ,  Yan-Heng Chen ,  Hsi-Chang Hsu ,  Chiang-Cheng Chang ,  Shih-Kuang Chiu

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.

Abstract translation: 公开了一种制造半导体封装件的方法，其包括以下步骤：提供具有释放层和依次在其上形成的粘合剂层的载体; 在所述粘合剂层上设置多个半导体芯片; 在粘合剂层上形成密封剂以封装半导体芯片; 将衬底设置在密封剂上; 将释放层暴露于通过载体的光，以便去除释放层和载体; 然后去除粘合剂层，从而有效地防止半导体芯片暴露于光，以避免对半导体芯片的任何光损坏。

公开(公告)号：US20170236783A1

公开(公告)日：2017-08-17

申请号：US15581799

申请日：2017-04-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yi-Wei Liu ,  Yan-Heng Chen ,  Mao-Hua Yeh ,  Hung-Wen Liu ,  Yi-Che Lai

IPC: H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/31053 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

公开(公告)号：US09548219B2

公开(公告)日：2017-01-17

申请号：US14584428

申请日：2014-12-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chung-Tang Lin ,  Chieh-Yuan Chi

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01L21/48 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0298 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/014

Abstract: A carrier structure is provided, which includes: a metal oxide plate having opposite first and second surfaces and a plurality of through holes penetrating the first and second surfaces; a plurality of conductive portions formed in the through holes, respectively; and a plurality of conductive pads formed on the first surface of the metal oxide plate, wherein each of the conductive pads is correspondingly positioned on and in contact with a plurality of the conductive portions so as to be electrically connected to the plurality of the conductive portions. By replacing a conventional silicon interposer with the metal oxide plate, the present invention eliminates the need to form through silicon vias as required in the prior art and therefore simplifies the fabrication process.

Abstract translation: 提供了一种载体结构，其包括：具有相对的第一和第二表面的金属氧化物板和穿过第一表面和第二表面的多个通孔; 分别形成在通孔中的多个导电部分; 以及形成在金属氧化物板的第一表面上的多个导电焊盘，其中每个导电焊盘相应地定位在多个导电部分上并与多个导电部分接触，以便电连接到多个导电部分 。 通过用金属氧化物板替代传统的硅插入器，本发明消除了如现有技术中所需要通过硅通孔形成的需要，因此简化了制造工艺。

公开(公告)号：US09515040B2

公开(公告)日：2016-12-06

申请号：US14736436

申请日：2015-06-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Chun-Tang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/10

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/18162

Abstract: A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.

Abstract translation: 提供了一种制造封装结构的方法，包括以下步骤：在第一载体上依次形成金属层和电介质层，其中电介质层具有暴露金属层部分的多个开口; 将电子元件经由其活性表面设置在电介质层上，并将金属球的多个导电元件安装在金属层的暴露部分上; 在所述电介质层上形成密封剂以封装所述电子元件和所述导电元件; 移除第一载体; 以及将所述金属层图案化成第一电路并在所述电介质层上形成第二电路，其中所述第二电路电连接到所述电子元件和所述第一电路。 本发明省去了常规的激光烧蚀工艺，以简化制造工艺，节省制造成本并提高产品的可靠性。

公开(公告)号：US20160141281A1

公开(公告)日：2016-05-19

申请号：US14873445

申请日：2015-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US09224646B2

公开(公告)日：2015-12-29

申请号：US14146171

申请日：2014-01-02

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Chieh-Yuan Chi ,  Hung-Wen Liu

IPC: H01L23/522 ,  H01L23/495 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76895 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract translation: 本发明公开了一种制造半导体封装的方法，包括提供具有绝缘层和至少嵌入绝缘层中的半导体元件的封装单元，其中半导体元件从绝缘层露出，并且形成在多个凹部中 绝缘层; 并且将再分布结构电连接到半导体元件。 凹陷部分的形成释放绝缘层的应力并防止绝缘层发生翘曲。

公开(公告)号：US20140183721A1

公开(公告)日：2014-07-03

申请号：US13846579

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yan-Heng Chen ,  Chiang-Cheng Chang ,  Jung-Pang Huang ,  Hsi-Chang Hsu ,  Yan-Yi Liao

IPC: H01L21/56 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105

Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.

Abstract translation: 提供一种半导体封装的制造方法，其包括以下步骤：提供具有粘合层和至少具有保护层的半导体元件的载体; 通过保护层将半导体元件设置在载体的粘合剂层上; 在用于封装半导体元件的载体的粘合剂层上形成密封剂; 去除载体和粘合剂层以将保护层暴露于密封剂; 以及去除所述保护层以使所述半导体元件暴露于所述密封剂。 由于半导体元件被保护层保护以防止在去除粘合剂层的过程中损坏，所以产品产率提高。