公开(公告)号：US09666557B2

公开(公告)日：2017-05-30

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/00 ,  H01L23/051 ,  H01L23/36 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

公开(公告)号：US20140353766A1

公开(公告)日：2014-12-04

申请号：US13905194

申请日：2013-05-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L25/065 ,  H01L23/051 ,  H01L23/34 ,  H01L23/36 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/04 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08237 ,  H01L2224/08257 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73151 ,  H01L2224/73251 ,  H01L2224/80898 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/922 ,  H01L2224/9221 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10454 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05 ,  H01L2224/29 ,  H01L2224/80 ,  H01L2924/00012

Abstract: A semiconductor assembly includes a substrate with electrically conductive regions and a semiconductor package. The semiconductor package includes a semiconductor die, first and second terminals, and a mold compound. The die has opposing first and second main surfaces, an edge disposed perpendicular to the first and second main surfaces, a first electrode at the first main surface, and a second electrode at the second main surface. The first terminal is attached to the first electrode. The second terminal is attached to the second electrode. The mold compound encloses at least part of the die and the first and second terminals so that each of the terminals has a side parallel with and facing away from the die that remains at least partly uncovered by the mold compound. The first and second terminals of the semiconductor package are connected to different ones of the electrically conductive regions of the substrate.

Abstract translation: 半导体组件包括具有导电区域的衬底和半导体封装。 半导体封装包括半导体管芯，第一和第二端子以及模具化合物。 模具具有相对的第一和第二主表面，垂直于第一和第二主表面设置的边缘，在第一主表面处的第一电极和在第二主表面处的第二电极。 第一端子附接到第一电极。 第二端子附接到第二电极。 模具化合物包围模具和第一和第二端子的至少一部分，使得每个端子具有与模具化合物保持至少部分未覆盖的模具平行并远离模具的一侧。 半导体封装的第一和第二端子连接到衬底的不同的导电区域。

公开(公告)号：US20180102300A1

公开(公告)日：2018-04-12

申请号：US15784439

申请日：2017-10-16

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Ming Kai Benny Goh

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/495

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

公开(公告)号：US09252063B2

公开(公告)日：2016-02-02

申请号：US14324295

申请日：2014-07-07

Applicant: Infineon Technologies AG

Inventor： Nee Wan Khoo ,  Lay Yeap Lim ,  Tian San Tan

IPC: H01L21/44 ,  H01L21/46 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L22/14 ,  H01L21/78 ,  H01L22/32 ,  H01L2224/97

Abstract: A leadframe strip includes a plurality of unit leadframes connected to a periphery of the leadframe strip, each unit leadframe having a die paddle, a plurality of leads and a semiconductor die attached to the die paddle. The leadframe strip is tested by electrically isolating at least the leads from the periphery of the leadframe strip such that at least some of the leads extend uninterrupted beyond a final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The semiconductor dies are tested, which includes probing the die paddles and the leads that extend uninterrupted beyond the final lead outline of the unit leadframes after electrical isolation from the periphery of the leadframe strip. The unit leadframes are severed from the leadframe strip along the final lead outline of the unit leadframes after testing the semiconductor dies.

Abstract translation: 引线框条包括连接到引线框带的周边的多个单元引线框架，每个单元引线框架具有管芯焊盘，多个引线和连接到管芯焊盘的半导体管芯。 引线框条通过至少将引线与引线框带的周边电隔离来进行测试，使得至少一些引线在与引线框带的外围电绝缘之后不间断延伸超过单元引线框架的最终引线轮廓。 测试半导体管芯，其包括在与引线框架条的周边电绝缘之后探测管芯焊盘和引线，其延伸不间断地超过单元引线框架的最终引线轮廓。 在测试半导体裸片之后，单元引线框架沿引线框架沿着单元引线框架的最终引线轮廓被切断。

公开(公告)号：US20150348864A1

公开(公告)日：2015-12-03

申请号：US14290046

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Ming Kai Benny Goh

IPC: H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L29/78 ,  H01L29/739 ,  H01L21/52 ,  H01L21/56 ,  H01L23/46

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

Abstract translation: 半导体封装系统包括具有两个或更多个端子的半导体芯片的半导体器件封装以及封装并电绝缘半导体芯片的保护结构。 两个或多个电连接到一个端子的电导体延伸到保护结构的外表面。 第一表面特征在半导体器件封装的外表面上。 该系统还包括可连接的包装扩展器，其具有第二表面特征，该第二表面特征构造成当第一表面特征与第二表面特征配合时与第一表面特征互锁，以便将包装延伸器固定到半导体器件封装。 当包装延伸器固定到半导体器件封装件上时，延伸部分邻接并延伸远离半导体器件封装的外表面。

公开(公告)号：US09153518B2

公开(公告)日：2015-10-06

申请号：US14015626

申请日：2013-08-30

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Teck Siang Hee

IPC: H01L23/32 ,  H01L23/48 ,  H01L23/057 ,  H01L23/28 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/32 ,  H01L23/057 ,  H01L23/16 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/48 ,  H01L24/06 ,  H01L24/29 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/42 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01R13/405 ,  H01R24/58 ,  H01R24/86 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor die having a plurality of terminals, a molding compound encapsulating the semiconductor die, and a pluggable lead dimensioned for insertion into an external receptacle. The pluggable lead protrudes from the molding compound and provides a separate electrical pathway for more than one terminal of the semiconductor die. The separate electrical pathways of the pluggable lead can be provided by electrical conductors isolated from one another by electrical insulator such as molding compound or other insulation material/medium.

Abstract translation: 半导体封装包括具有多个端子的半导体管芯，封装半导体管芯的模制化合物和用于插入到外部插座中的可插拔引线。 可插拔引线从模制化合物突出并且为半导体管芯的多于一个端子提供单独的电路径。 可插拔引线的单独电路可以由电绝缘体（例如模塑料或其它绝缘材料/介质）彼此隔离的电导体提供。

公开(公告)号：US20150279757A1

公开(公告)日：2015-10-01

申请号：US14242114

申请日：2014-04-01

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L23/492 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49572 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/09 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor die package includes first, second and third metal blocks insulated from one another. The first metal block has a thinner inner section, a first thicker outer section at a first end of the thinner inner section and a second thicker outer section at a second end of the thinner inner section opposing the first end. The second metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. The third metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. A semiconductor die has a first terminal attached to the thinner inner section of the first metal block, a second terminal attached to the thinner inner section of the second metal block, and a third terminal attached to the thinner inner section of the third metal block.

Abstract translation: 半导体管芯封装包括彼此绝缘的第一，第二和第三金属块。 第一金属块具有更薄的内部部分，在较薄内部部分的第一端处的第一较厚外部部分和在较薄内部部分的与第一端部相对的第二端处的第二较厚外部部分。 第二金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 第三金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 半导体管芯具有附接到第一金属块的较薄内部的第一端子，附接到第二金属块的较薄内部的第二端子和附接到第三金属块的较薄内部的第三端子。

公开(公告)号：US09892991B2

公开(公告)日：2018-02-13

申请号：US14290046

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long ,  Ming Kai Benny Goh

IPC: H01L23/367 ,  H01L23/46 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L29/739 ,  H01L29/78 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/473

CPC classification number: H01L23/3672 ,  H01L21/4871 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/46 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L29/7395 ,  H01L29/7802 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor packaging system includes a semiconductor device package having a semiconductor chip with two or more terminals and a protective structure encapsulating and electrically insulating the semiconductor chip. Two or more electrical conductors that are each electrically connected to one of the terminals extend to an outer surface of the protective structure. A first surface feature is on an exterior surface of the semiconductor device package. The system further includes a connectable package extender having a second surface feature configured to interlock with the first surface feature when the first surface feature is mated with the second surface feature so as to secure the package extender to the semiconductor device package. An extension portion adjoins and extends away from the exterior surface of the semiconductor device package when the package extender is secured to the semiconductor device package.

公开(公告)号：US09508625B2

公开(公告)日：2016-11-29

申请号：US14242114

申请日：2014-04-01

Applicant: Infineon Technologies AG

Inventor： Tian San Tan ,  Theng Chao Long

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/3157 ,  H01L23/492 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49572 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/09 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor die package includes first, second and third metal blocks insulated from one another. The first metal block has a thinner inner section, a first thicker outer section at a first end of the thinner inner section and a second thicker outer section at a second end of the thinner inner section opposing the first end. The second metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. The third metal block has a thicker outer section and a thinner inner section protruding inward from the thicker outer section. A semiconductor die has a first terminal attached to the thinner inner section of the first metal block, a second terminal attached to the thinner inner section of the second metal block, and a third terminal attached to the thinner inner section of the third metal block.

Abstract translation: 半导体管芯封装包括彼此绝缘的第一，第二和第三金属块。 第一金属块具有更薄的内部部分，在较薄内部部分的第一端处的第一较厚外部部分和在较薄内部部分的与第一端部相对的第二端处的第二较厚外部部分。 第二金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 第三金属块具有较厚的外部部分和从较厚的外部部分向内突出的较薄的内部部分。 半导体管芯具有附接到第一金属块的较薄内部的第一端子，附接到第二金属块的较薄内部的第二端子和附接到第三金属块的较薄内部的第三端子。

公开(公告)号：US09490199B2

公开(公告)日：2016-11-08

申请号：US14194916

申请日：2014-03-03

Applicant: Infineon Technologies AG

Inventor： Theng Chao Long ,  Tian San Tan ,  Wan Yee Ng ,  Kong Sin Chong

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49844 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2225/1017 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15331 ,  H01L2924/15333 ,  H01L2924/181 ,  H05K1/0287 ,  H05K1/029 ,  H05K1/181 ,  H05K2201/0305 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An interposer for establishing a vertical connection between semiconductor packages includes an electrically insulating substrate having a first main side and a second main side opposite the first main side, a plurality of first electrical conductors at the first main side of the substrate, a plurality of second electrical conductors at the second main side of the substrate, and a programmable connection matrix at one or both main sides of the substrate. The programmable connection matrix includes programmable junctions configured to open or close electrical connections between different ones of the first electrical conductors and different ones of the second electrical conductors upon programming of the junctions.

Abstract translation: 用于在半导体封装之间建立垂直连接的插入件包括具有第一主侧和与第一主侧相对的第二主侧的电绝缘基板，在基板的第一主侧的多个第一电导体，多个第二主体 在基板的第二主侧的电导体和在基板的一个或两个主侧的可编程连接矩阵。 可编程连接矩阵包括被配置为在编程接合点时打开或闭合不同的第一电导体和不同的第二电导体之间的电连接的可编程结。