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公开(公告)号：US20120273940A1
公开(公告)日：2012-11-01
申请号：US13336948
申请日：2011-12-23
申请人： Seung Hee JO
发明人： Seung Hee JO
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/18 , H01L2224/0401 , H01L2224/05548 , H01L2224/11462 , H01L2224/13025 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13188 , H01L2224/14131 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/2732 , H01L2224/29011 , H01L2224/29013 , H01L2224/29188 , H01L2224/2919 , H01L2224/30151 , H01L2224/32145 , H01L2224/48227 , H01L2224/73257 , H01L2224/80099 , H01L2224/81203 , H01L2224/81896 , H01L2224/83191 , H01L2224/8384 , H01L2224/83855 , H01L2224/9202 , H01L2225/0651 , H01L2225/06517 , H01L2225/06544 , H01L2225/06558 , H01L2225/06565 , H01L2924/00013 , H01L2924/01029 , H01L2924/01322 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/05442 , H01L2924/00014 , H01L2924/0665 , H01L2924/01082 , H01L2924/01047 , H01L2924/01083 , H01L2924/01051 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/3512 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor apparatus includes a first chip comprising a first bonding pad and a dielectric layer exposes a portion of the first bonding pad; a first bonding layer covering entirely or partially the first front side of the first chip, a second chip comprising a second bonding pad and a through-silicon via, and a conductive projection formed over the second bonding pad. The dielectric layer is formed on of the first chip, a second back side of the second chip is bonded to the first front side of the first chip by the medium of the first bonding layer, and the second bonding pad formed on a second front side of the second chip is coupled to the first bonding pad by the through-silicon via.
摘要翻译： 半导体装置包括：第一芯片，包括第一焊盘和介电层，暴露第一焊盘的一部分; 完全或部分地覆盖第一芯片的第一前侧的第一粘合层，包括第二焊盘和穿硅通孔的第二芯片以及形成在第二焊盘上的导电突起。 电介质层形成在第一芯片上，第二芯片的第二背面通过第一接合层的介质接合到第一芯片的第一前侧，并且第二焊盘形成在第二正面 的第二芯片通过硅通孔耦合到第一焊盘。
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公开(公告)号：US07554206B2
公开(公告)日：2009-06-30
申请号：US11607372
申请日：2006-12-01
申请人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart E. Wilson , Wael Zohni , Yoichi Kubota , Jesse Burl Thompson
发明人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart E. Wilson , Wael Zohni , Yoichi Kubota , Jesse Burl Thompson
IPC分类号： H01L23/52 , H01L23/48 , H01L23/40 , H01L23/485 , H01L23/498
CPC分类号： H01L23/49811 , G01R1/06744 , G01R1/0735 , H01L21/563 , H01L23/4985 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/05599 , H01L2224/0603 , H01L2224/131 , H01L2224/13147 , H01L2224/13187 , H01L2224/13188 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/1357 , H01L2224/136 , H01L2224/1403 , H01L2224/16 , H01L2224/17 , H01L2224/1703 , H01L2224/48091 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2224/13099 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic assembly includes a microelectronic package having a microelectronic element with faces and contacts, a flexible substrate spaced from and overlying a first face of the microelectronic element, and a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, at least some of the conductive posts being electrically interconnected with the microelectronic element. The package includes a plurality of support elements disposed between the microelectronic element and the substrate and supporting the flexible substrate over the microelectronic element. At least some of the conductive posts are offset from the support elements. The assembly includes a circuitized substrate having conductive pads confronting the conductive posts of the microelectronic package, whereby the conductive posts are electrically interconnected with the conductive pads.
摘要翻译： 微电子组件包括具有微电子元件的微电子封装，所述微电子元件具有面和触点，与微电子元件的第一面间隔开并覆盖所述微电子元件的第一面的柔性基板以及从所述柔性基板延伸并远离所述第一面突出的多个导电柱 微电子元件，至少一些导电柱与微电子元件电互连。 所述封装包括设置在所述微电子元件和所述基板之间的多个支撑元件，并且在所述微电子元件上支撑所述柔性基板。 至少一些导电柱从支撑元件偏移。 组件包括具有面对微电子封装的导电柱的导电焊盘的电路化衬底，由此导电柱与导电焊盘电互连。
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公开(公告)号：US09607716B2
公开(公告)日：2017-03-28
申请号：US14248480
申请日：2014-04-09
IPC分类号： G11C11/412 , G11C11/413 , G11C29/50 , G11C29/00 , G11C29/02 , H01L23/538 , H01L25/065 , H01L23/48 , H01L23/498 , H01L23/00 , H01L25/18
CPC分类号： G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
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公开(公告)号：US07176043B2
公开(公告)日：2007-02-13
申请号：US11014439
申请日：2004-12-16
申请人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart E. Wilson , Wael Zohni , Yoichi Kubota , Jesse Burl Thompson
发明人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart E. Wilson , Wael Zohni , Yoichi Kubota , Jesse Burl Thompson
IPC分类号： H01L21/66
CPC分类号： H01L23/49811 , G01R1/06744 , G01R1/0735 , H01L21/563 , H01L23/4985 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/05599 , H01L2224/0603 , H01L2224/131 , H01L2224/13147 , H01L2224/13187 , H01L2224/13188 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/1357 , H01L2224/136 , H01L2224/1403 , H01L2224/16 , H01L2224/17 , H01L2224/1703 , H01L2224/48091 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2224/13099 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic package includes a microelectronic element having faces and contacts and a flexible substrate spaced from and overlying a first face of the microelectronic element. The package also includes a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, wherein at least some of the conductive posts are electrically interconnected with the microelectronic element, and a plurality of support elements supporting the flexible substrate over the microelectronic element. The conductive posts are offset from the support elements to facilitate flexure of the substrate and movement of the posts relative to the microelectronic element.
摘要翻译： 微电子封装包括具有面和触点的微电子元件和与微电子元件的第一面间隔开并且覆盖其上的柔性基板。 该封装还包括从柔性基板延伸并从远离微电子元件的第一面突出的多个导电柱，其中至少一些导电柱与微电子元件电互连，以及多个支撑元件 微电子元件上的柔性衬底。 导电柱从支撑元件偏移以便于基板的挠曲和柱相对于微电子元件的移动。
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公开(公告)号：US20230238344A1
公开(公告)日：2023-07-27
申请号：US17888915
申请日：2022-08-16
发明人： Tomohiro SAITO
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/13076 , H01L2224/13144 , H01L2224/13124 , H01L2224/13147 , H01L2224/13109 , H01L2224/13184 , H01L2224/13166 , H01L2224/13164 , H01L2224/13188 , H01L2224/16145 , H01L2924/05442 , H01L2924/05042 , H01L2924/04941 , H01L2924/1306 , H01L2924/1461 , H01L2924/1436 , H01L2924/12041 , H01L2924/12042 , H01L2224/81193 , H01L2224/81201
摘要： An electronic device includes a first structure body and a second structure body. The first structure body includes a first base body, a first bonding electrode and a first hard part. The second structure body includes a second base body, and a second bonding electrode. The first bonding electrode and the second bonding electrode are bonded to each other between the first base body and the second base body. The first hard part is located between the first base body and the second base body. The first hard part is positioned within an area in which the first bonding electrode is located when viewed along a first direction. The first direction is from the first base body toward the first bonding electrode. The first hard part has a higher hardness than the first bonding electrode.
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公开(公告)号：US20150179280A1
公开(公告)日：2015-06-25
申请号：US14138838
申请日：2013-12-23
CPC分类号： G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
摘要翻译： 公开了一种用于测试连接到并布置在用于连接缺陷的逻辑芯片的顶部上的多个存储器芯片的堆叠存储器件的方法。 该方法可以包括通过将数据值写入存储器芯片中的第一位置，从第一位置读取数据值，检测第一位错误并记录第一位错误的位数来测试存储器芯片。 该方法还可以包括通过将数据值写入存储器芯片中的第二位置来测试存储器芯片，从存储器芯片中的第二位置读取数据值，检测第二位错误并记录第二位的位数 错误。 该方法还可以包括用备用连接替换与第一和第二位错误共同的连接。
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公开(公告)号：US20050181544A1
公开(公告)日：2005-08-18
申请号：US11014439
申请日：2004-12-16
申请人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart Wilson , Wael Zohni , Yoichi Kubota , Jesse Thompson
发明人： Belgacem Haba , Masud Beroz , Ronald Green , Ilyas Mohammed , Stuart Wilson , Wael Zohni , Yoichi Kubota , Jesse Thompson
IPC分类号： H01L21/44
CPC分类号： H01L23/49811 , G01R1/06744 , G01R1/0735 , H01L21/563 , H01L23/4985 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/73 , H01L2224/0401 , H01L2224/05599 , H01L2224/0603 , H01L2224/131 , H01L2224/13147 , H01L2224/13187 , H01L2224/13188 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/1357 , H01L2224/136 , H01L2224/1403 , H01L2224/16 , H01L2224/17 , H01L2224/1703 , H01L2224/48091 , H01L2224/73203 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/83194 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2224/13099 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A microelectronic package includes a microelectronic element having faces and contacts and a flexible substrate spaced from and overlying a first face of the microelectronic element. The package also includes a plurality of conductive posts extending from the flexible substrate and projecting away from the first face of the microelectronic element, wherein at least some of the conductive posts are electrically interconnected with the microelectronic element, and a plurality of support elements supporting the flexible substrate over the microelectronic element. The conductive posts are offset from the support elements to facilitate flexure of the substrate and movement of the posts relative to the microelectronic element.
摘要翻译： 微电子封装包括具有面和触点的微电子元件和与微电子元件的第一面间隔开并且覆盖其上的柔性基板。 该封装还包括从柔性基板延伸并从远离微电子元件的第一面突出的多个导电柱，其中至少一些导电柱与微电子元件电互连，以及多个支撑元件 微电子元件上的柔性衬底。 导电柱从支撑元件偏移以便于基板的挠曲和柱相对于微电子元件的移动。
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公开(公告)号：US20240145420A1
公开(公告)日：2024-05-02
申请号：US17975654
申请日：2022-10-28
申请人： Intel Corporation
IPC分类号： H01L23/00
CPC分类号： H01L24/26 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/13101 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13188 , H01L2224/1413 , H01L2224/16227 , H01L2224/26175 , H01L2224/27013 , H01L2224/2732 , H01L2224/29011 , H01L2224/29013 , H01L2224/29014 , H01L2224/30051 , H01L2224/3016 , H01L2224/32227 , H01L2224/73103 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/831 , H01L2224/83193 , H01L2924/01037 , H01L2924/01055 , H01L2924/01087 , H01L2924/0133 , H01L2924/0543 , H01L2924/0665 , H01L2924/07025 , H01L2924/0715 , H01L2924/1432 , H01L2924/1434
摘要： The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.
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公开(公告)号：US09263157B2
公开(公告)日：2016-02-16
申请号：US14138838
申请日：2013-12-23
IPC分类号： G11C29/50 , G11C29/00 , G11C29/02 , H01L23/538 , H01L25/065
CPC分类号： G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
摘要翻译： 公开了一种用于测试连接到并布置在用于连接缺陷的逻辑芯片的顶部上的多个存储器芯片的堆叠存储器件的方法。 该方法可以包括通过将数据值写入存储器芯片中的第一位置，从第一位置读取数据值，检测第一位错误并记录第一位错误的位数来测试存储器芯片。 该方法还可以包括通过将数据值写入存储器芯片中的第二位置来测试存储器芯片，从存储器芯片中的第二位置读取数据值，检测第二位错误并记录第二位的位数 错误。 该方法还可以包括用备用连接替换与第一和第二位错误共同的连接。
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公开(公告)号：US20150179285A1
公开(公告)日：2015-06-25
申请号：US14248480
申请日：2014-04-09
IPC分类号： G11C29/50 , H01L25/065 , H01L23/538 , G11C29/00
CPC分类号： G11C29/50004 , G11C29/022 , G11C29/025 , G11C29/70 , G11C29/702 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/13188 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/014
摘要： A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.
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