公开(公告)号：US09716066B2

公开(公告)日：2017-07-25

申请号：US14779022

申请日：2013-06-29

申请人： Intel Corporation

发明人： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

公开(公告)号：US20160049371A1

公开(公告)日：2016-02-18

申请号：US14779022

申请日：2013-06-29

申请人： INTEL CORPORATION

发明人： Kevin J. Lee ,  James Y. Jeong ,  Hsiao-Kang Chang ,  John Muirhead ,  Adwait Telang ,  Puneesh Puri ,  Jiho Kang ,  Nitin M. Patel

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

摘要： A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

摘要翻译： 描述了三维互连结构和制造方法，其中金属再分布层（RDL）与硅通孔（TSV）集成并且使用“平板通过抗蚀剂”型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

申请人： Intel Corporation

发明人： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

摘要： Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.