Invention Grant
- Patent Title: High density substrate routing in package
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Application No.: US18373849Application Date: 2023-09-27
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Publication No.: US12051667B2Publication Date: 2024-07-30
- Inventor: Weng Hong Teh , Chia-Pin Chiu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- The original application number of the division: US13707159 2012.12.06
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/31 ; H01L23/50 ; H01L25/16 ; H01L25/18 ; H01L21/56

Abstract:
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
Public/Granted literature
- US20240021562A1 HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE Public/Granted day:2024-01-18
Information query
IPC分类: