公开(公告)号：US09171816B2

公开(公告)日：2015-10-27

申请号：US14663689

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract translation: 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US20140159228A1

公开(公告)日：2014-06-12

申请号：US13707159

申请日：2012-12-06

Applicant: Weng Hong Teh ,  Chia-Pin Chiu

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L21/56 ,  H01L23/522

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract translation: 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US11810884B2

公开(公告)日：2023-11-07

申请号：US17570255

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/255 ,  H01L2224/2512 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20160079196A1

公开(公告)日：2016-03-17

申请号：US14922425

申请日：2015-10-26

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20240339428A1

公开(公告)日：2024-10-10

申请号：US18749274

申请日：2024-06-20

Applicant: Intel Corporation

Inventor： Weng Hong TEH ,  Chia-Pin CHIU

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20170053887A1

公开(公告)日：2017-02-23

申请号：US15255351

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/50 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract translation: 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US20240321786A1

公开(公告)日：2024-09-26

申请号：US18735151

申请日：2024-06-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/66 ,  H01L23/291 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L2223/6677 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/255 ,  H01L2224/29024 ,  H01L2224/32146

Abstract: A manufacturing method of a package structure includes: providing a carrier substrate with an integrated circuit (IC) die, where the IC die is disposed in a cavity of the carrier substrate, and a thermally conductive layer is formed in the cavity to separate the IC die from the carrier substrate; forming a redistribution structure on a first side of the carrier substrate, where the redistribution structure is electrically coupled to the IC die; forming an antenna pattern over the redistribution structure; forming a patterned dielectric layer with an opening on a second side of the carrier substrate opposite to the first side, where a portion of the second side of the carrier substrate is exposed by the opening; and forming an underfill to be in thermal contact with the carrier substrate, where the underfill extends outward beyond an edge of the carrier substrate.

公开(公告)号：US12051667B2

公开(公告)日：2024-07-30

申请号：US18373849

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/50 ,  H01L25/16 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L21/568 ,  H01L23/3128 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US12033963B2

公开(公告)日：2024-07-09

申请号：US17461957

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/66 ,  H01L23/291 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L2223/6677 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/255 ,  H01L2224/29024 ,  H01L2224/32146

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a carrier substrate, an integrated circuit (IC) die thermally coupled to the carrier substrate through a thermally conductive layer, an antenna pattern disposed over the carrier substrate and the IC die, a redistribution structure disposed between the antenna pattern and the IC die, and an underfill disposed below and thermally coupled to the carrier substrate. The antenna pattern is electrically coupled to the IC die.

公开(公告)号：US20190139926A1

公开(公告)日：2019-05-09

申请号：US16239670

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H01L23/31 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.