公开(公告)号：US08937382B2

公开(公告)日：2015-01-20

申请号：US13169162

申请日：2011-06-27

申请人： Weng Hong Teh ,  John S. Guzek

发明人： Weng Hong Teh ,  John S. Guzek

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

公开(公告)号：US20140264830A1

公开(公告)日：2014-09-18

申请号：US13801859

申请日：2013-03-13

申请人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

发明人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

IPC分类号： H01L23/498

CPC分类号： H01L23/49822 ,  H01L21/76807 ,  H01L21/7681 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/19 ,  H01L2221/1026 ,  H01L2224/12105 ,  H01L2924/18162

摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。

公开(公告)号：US20140083858A1

公开(公告)日：2014-03-27

申请号：US13624288

申请日：2012-09-21

申请人： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

发明人： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

IPC分类号： B01D43/00 ,  H05K3/30

CPC分类号： H05K1/0272 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0212 ,  H05K1/185 ,  H05K3/0097 ,  H05K2201/097 ,  H05K2203/1536 ,  H05K2203/308 ,  Y10T29/4913

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将微流体管芯附接到封装结构，其中微流体管芯包括可以与设置在封装结构内的信号焊盘耦合的多个不对称电极。

公开(公告)号：US20130270715A1

公开(公告)日：2013-10-17

申请号：US13996495

申请日：2011-12-15

申请人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L23/48

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US09708178B2

公开(公告)日：2017-07-18

申请号：US13995924

申请日：2011-12-30

申请人： Weng Hong Teh ,  Robert L. Sankman

发明人： Weng Hong Teh ,  Robert L. Sankman

IPC分类号： B81B7/02 ,  B81B7/00 ,  B81C1/00 ,  H01L23/00 ,  H05K1/18

CPC分类号： B81B7/0006 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00134 ,  B81C1/0023 ,  H01L23/48 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16135 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2224/82

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.

公开(公告)号：US09429427B2

公开(公告)日：2016-08-30

申请号：US13720876

申请日：2012-12-19

申请人： Qing Ma ,  Feras Eid ,  Kevin Lin ,  Johanna M. Swan ,  Weng Hong Teh ,  Valluri R. Rao

发明人： Qing Ma ,  Feras Eid ,  Kevin Lin ,  Johanna M. Swan ,  Weng Hong Teh ,  Valluri R. Rao

IPC分类号： G01C19/00 ,  G01C19/56 ,  G01C19/5776

CPC分类号： G01C19/56 ,  G01C19/5776

摘要： This invention relates to inductive inertial sensors employing a magnetic drive and/or sense architecture. In embodiments, translational gyroscopes utilize a conductive coil made to vibrate in a first dimension as a function of a time varying current driven through the coil in the presence of a magnetic field. Sense coils register an inductance that varies as a function of an angular velocity in a second dimension. In embodiments, the vibrating coil causes first and second mutual inductances in the sense coils to deviate from each other as a function of the angular velocity. In embodiments, self-inductances associated with a pair of meandering coils vary as a function of an angular velocity in a second dimension. In embodiments, package build-up layers are utilized to fabricate the inductive inertial sensors, enabling package-level integrated inertial sensing advantageous in small form factor computing platforms, such as mobile devices.

摘要翻译： 本发明涉及采用磁驱动和/或感测架构的感应惯性传感器。 在实施例中，平移陀螺仪利用在第一维度中制成的导电线圈作为在存在磁场的情况下驱动通过线圈的时变电流的函数。 感应线圈记录在第二维度上作为角速度的函数变化的电感。 在实施例中，振动线圈使得感测线圈中的第一和第二互感器作为角速度的函数彼此偏离。 在实施例中，与一对曲折线圈相关联的自感量作为第二维度中的角速度的函数而变化。 在实施例中，使用封装积层来制造感应惯性传感器，使得能够在诸如移动设备的小尺寸计算平台中有利的封装级集成惯性感测。

公开(公告)号：US09299660B2

公开(公告)日：2016-03-29

申请号：US13977473

申请日：2011-11-14

申请人： Weng Hong Teh ,  Shan Zhong

发明人： Weng Hong Teh ,  Shan Zhong

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/82 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/5384 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0331 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A process of bumping a die backside includes opening a recess in a die backside film (DBF) to expose a through-silicon via (TSV) contact in a die, followed by filling the recess with a conductive material that contacts the TSV contact. Added solder is coupled to the conductive material at a level of the DBF. A subsequent die is coupled to the first die at the added solder to form an electrical coupling consisting of the TSV contact, the conductive material, and the added solder, an electrical bump coupled to the subsequent die. Apparatus and computer systems are assembled using the process.

摘要翻译： 冲模模具背面的过程包括在模具背面薄膜（DBF）中打开凹部以暴露模具中的硅 - 硅通孔（TSV）接触，然后用与TSV触点接触的导电材料填充凹部。 添加的焊料在DBF的水平处耦合到导电材料。 随后的管芯在添加的焊料处耦合到第一管芯，以形成由TSV接触，导电材料和添加的焊料组成的电耦合，耦合到后续管芯的电凸点。 装置和计算机系统使用该过程组装。

公开(公告)号：US20140169800A1

公开(公告)日：2014-06-19

申请号：US13717185

申请日：2012-12-17

申请人： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

发明人： Feras Eid ,  Johanna Swan ,  Weng Hong Teh

IPC分类号： H04B10/40 ,  F21V21/00 ,  H01L33/00

CPC分类号： H01S5/02272 ,  H01L21/568 ,  H01L24/18 ,  H01L24/19 ,  H01L25/167 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2924/12042 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02288 ,  H01S5/02292 ,  H01S5/183 ,  H01S5/18305 ,  H01L2924/00

摘要： This disclosure relates generally to an electronic package that can include a die and a dielectric layer at least partially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the dielectric layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic package different from the first major surface.

摘要翻译： 本公开一般涉及一种电子封装，其可以包括至少部分地包封管芯的管芯和电介质层。 电互连可以电耦合到管芯并且至少部分地通过电介质层。 光发射器可以用电互连的第一个电耦合到管芯，并且被配置为从电子封装的第一主表面发射光。 焊料凸块可以用电互连的第二个电耦合到管芯，并且位于电子封装的不同于第一主表面的第二主表面上。

公开(公告)号：US20140165723A1

公开(公告)日：2014-06-19

申请号：US13720876

申请日：2012-12-19

申请人： Qing MA ,  Feras EID ,  Kevin LIN ,  Johanna M. SWAN ,  Weng Hong TEH ,  Valluri R. RAO

发明人： Qing MA ,  Feras EID ,  Kevin LIN ,  Johanna M. SWAN ,  Weng Hong TEH ,  Valluri R. RAO

IPC分类号： G01C19/5635

CPC分类号： G01C19/56 ,  G01C19/5776

摘要： This invention relates to inductive inertial sensors employing a magnetic drive and/or sense architecture. In embodiments, translational gyroscopes utilize a conductive coil made to vibrate in a first dimension as a function of a time varying current driven through the coil in the presence of a magnetic field. Sense coils register an inductance that varies as a function of an angular velocity in a second dimension. In embodiments, the vibrating coil causes first and second mutual inductances in the sense coils to deviate from each other as a function of the angular velocity. In embodiments, self-inductances associated with a pair of meandering coils vary as a function of an angular velocity in a second dimension. In embodiments, package build-up layers are utilized to fabricate the inductive inertial sensors, enabling package-level integrated inertial sensing advantageous in small form factor computing platforms, such as mobile devices.

摘要翻译： 本发明涉及采用磁驱动和/或感测架构的感应惯性传感器。 在实施例中，平移陀螺仪利用在第一维度中制成的导电线圈作为在存在磁场的情况下驱动通过线圈的时变电流的函数。 感应线圈记录在第二维度上作为角速度的函数变化的电感。 在实施例中，振动线圈使得感测线圈中的第一和第二互感器作为角速度的函数彼此偏离。 在实施例中，与一对曲折线圈相关联的自感量作为第二维度中的角速度的函数而变化。 在实施例中，使用封装积层来制造感应惯性传感器，使得能够在诸如移动设备的小尺寸计算平台中有利的封装级集成惯性感测。

公开(公告)号：US20130277865A1

公开(公告)日：2013-10-24

申请号：US13977183

申请日：2011-10-31

申请人： Weng Hong Teh ,  John S. Guzek ,  Shan Zhong

发明人： Weng Hong Teh ,  John S. Guzek ,  Shan Zhong

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

摘要翻译： 描述了封装组件和封装集成电路芯片的方法。 公开的封装组件具有包括IC芯片的间隔件和凹陷区域。 提供了建立结构，使得能够例如三维（3D）封装（或封装（SiP）或多芯片模块系统）），片上3D封装和混合3D绑定。 本发明的实施例可以用于例如创建逻辑到存储器，存储器到存储器和逻辑到逻辑接口堆叠组件。