Invention Grant
- Patent Title: Stacked silicon die architecture with mixed flipcip and wirebond interconnect
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Application No.: US16645744Application Date: 2017-12-30
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Publication No.: US11410919B2Publication Date: 2022-08-09
- Inventor: Robert L. Sankman , Sanka Ganesan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2017/069157 WO 20171230
- International Announcement: WO2019/133019 WO 20190704
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48 ; H01L23/31 ; H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a base die disposed on an interposer. The semiconductor package also has a plurality of dies on top of one another to form a stack on the base die. Each die has a top surface and a bottom surface that is opposite from the top surface, and each die has one or more die contacts on at least one of the top surface and the bottom surface that are each electrically coupled to at least one die contact of the base die with one or more wire bonds. The semiconductor package includes a mold layer disposed over and around the plurality of dies, the base die, and the one or more wire bonds. The base die may have a first surface area that exceeds a second surface area of the plurality of stacked dies.
Public/Granted literature
- US20200273783A1 STACKED SILICON DIE ARCHITECTURE WITH MIXED FLIPCIP AND WIREBOND INTERCONNECT Public/Granted day:2020-08-27
Information query
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