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    ULTRASOUND ASSISTED IMMERSION COOLING
    2.
    发明申请
    ULTRASOUND ASSISTED IMMERSION COOLING 有权
    超声波辅助冷却

    公开(公告)号：US20160286694A1

    公开(公告)日：2016-09-29

    申请号：US14668331

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Shankar Krishnan ,  Richard C. Stamey ,  Brian S. Jarrett ,  Geoffrey G. Von Allmen

    IPC: H05K7/20

    CPC classification number: H05K7/20836 ,  H01L23/44 ,  H05K7/20236 ,  H05K7/20272 ,  H05K7/20281 ,  H05K7/203 ,  H05K7/20772 ,  H05K7/20781 ,  H05K7/2079

    Abstract: Apparatuses, methods and storage media associated with cooling one or more heat-generating components of an electronic device are disclosed herein. In embodiments, an electronic device may include a tank that may include a dielectric fluid and one or more heat-generating components. The electronic device may further include one or more transducers coupled with the tank. The transducers may be configured to generate an ultrasonic wave that controls movement of the dielectric fluid at a location within the tank. Other embodiments may be described and/or claimed.

    Abstract translation: 本文公开了与冷却电子设备的一个或多个发热部件相关联的装置，方法和存储介质。 在实施例中，电子设备可以包括可以包括介电流体和一个或多个发热部件的罐。 电子设备还可以包括与罐相耦合的一个或多个换能器。 换能器可以被配置为产生超声波，其控制介质流体在罐内的位置的运动。 可以描述和/或要求保护其他实施例。

    Multi-use package architecture
    3.
    发明授权
    Multi-use package architecture 有权

    公开(公告)号：US11929295B2

    公开(公告)日：2024-03-12

    申请号：US17677843

    申请日：2022-02-22

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

    CPC classification number: H01L23/3121 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/82 ,  H01L2924/01029 ,  H01L2924/1811

    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

    MULTI-USE PACKAGE ARCHITECTURE
    6.
    发明申请
    MULTI-USE PACKAGE ARCHITECTURE 有权

    公开(公告)号：US20220181227A1

    公开(公告)日：2022-06-09

    申请号：US17677843

    申请日：2022-02-22

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

    IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

    MODULAR PRINTED CIRCUIT BOARD
    8.
    发明申请
    MODULAR PRINTED CIRCUIT BOARD 有权
    模块化印刷电路板

    公开(公告)号：US20150373847A1

    公开(公告)日：2015-12-24

    申请号：US14496876

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： Kevin E. Wells ,  Richard C. Stamey

    IPC: H05K1/11 ,  H05K3/42 ,  G06F1/16 ,  H05K3/36 ,  H05K1/02 ,  H05K7/02

    CPC classification number: G06F1/16 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/421 ,  H05K3/4694 ,  H05K2201/041 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/10719 ,  Y02P70/613 ,  Y10T29/49128 ,  H01L2924/00

    Abstract: Described are apparatuses for modular printed circuit boards (PCB) and methods for producing modular PCBs. An apparatus may include a first PCB module with a first pattern of routing structures on one or more layers of the first PCB module. The apparatus may further include a second PCB module with a second pattern of routing structures on one or more layers of the second PCB module. The second pattern of routing structures may be aligned with and electrically coupled to the first pattern of routing structures without connectors. Other embodiments may be described and/or claimed.

    Abstract translation: 描述了用于模块化印刷电路板（PCB）的装置和用于制造模块化PCB的方法。 装置可以包括具有在第一PCB模块的一个或多个层上的路由结构的第一图案的第一PCB模块。 该装置还可以包括具有在第二PCB模块的一个或多个层上的路由结构的第二图案的第二PCB模块。 路由结构的第二模式可以与没有连接器的路由结构的第一模式对准并电耦合。 可以描述和/或要求保护其他实施例。

    MULTI-USE PACKAGE ARCHITECTURE
    10.
    发明申请
    MULTI-USE PACKAGE ARCHITECTURE 审中-公开

    公开(公告)号：US20190287872A1

    公开(公告)日：2019-09-19

    申请号：US15925429

    申请日：2018-03-19

    Applicant: INTEL CORPORATION

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Richard C. Stamey ,  Chu Aun Lim ,  Jimin Yao

    IPC: H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/00

    Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

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