公开(公告)号：US11705377B2

公开(公告)日：2023-07-18

申请号：US17720202

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Robert L. Sankman ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Amruthavalli P. Alur ,  Yikang Deng ,  Eric J. Li

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1432 ,  H01L2924/1434

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220130763A1

公开(公告)日：2022-04-28

申请号：US17572167

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US11217573B2

公开(公告)日：2022-01-04

申请号：US16809515

申请日：2020-03-04

Applicant: Intel Corporation

Inventor： Suresh V. Pothukuchi ,  Andrew Alduino ,  Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Ling Liao ,  Harinadh Potluri ,  David M. Bond ,  Sushrutha Reddy Gujjula ,  Donald Tiendung Tran ,  David Hui ,  Vladimir Tamarkin

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/473 ,  H01L23/538 ,  H04Q11/00

Abstract: Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

公开(公告)号：US10978423B2

公开(公告)日：2021-04-13

申请号：US15781998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Ravindranath V. Mahajan

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L29/66 ,  H01L29/40 ,  H01L23/58

Abstract: A package assembly includes a substrate extending from a first substrate end to a second substrate end. A plurality of conductive traces extend along the substrate. A plurality of contacts are coupled with the respective conductive traces of the plurality of conductive traces. Each of the contacts of the plurality of contacts includes a contact pad coupled with a respective conductive trace of the plurality of conductive traces, and a contact post coupled with the contact pad, the contact post extends from the contact pad. A package cover layer is coupled over the plurality of contact posts. The plurality of contact posts are configured to penetrate the package cover layer and extend to a raised location above the package cover layer.

公开(公告)号：US10366951B2

公开(公告)日：2019-07-30

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20180350737A1

公开(公告)日：2018-12-06

申请号：US16002740

申请日：2018-06-07

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US09691711B2

公开(公告)日：2017-06-27

申请号：US15055120

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.

公开(公告)号：US09275955B2

公开(公告)日：2016-03-01

申请号：US14132774

申请日：2013-12-18

Applicant: INTEL CORPORATION

Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC: H01L23/28 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  H01L23/14 ,  H01L23/31 ,  H01L23/433 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有分别具有第一和第二输入/输出（I / O）互连结构的第一和第二裸片的集成电路（IC）封装。 IC封装可以包括具有分别耦合到第一和第二I / O互连结构的一部分的第一和第二电路由特征的桥。 在实施例中，第一和第二电路由特征可以设置在桥的一侧; 并且第三电路布线特征可以设置在相对侧上。 第一和第二电路由特征可以被配置为在第一管芯和第二管芯之间路由电信号，并且第三电路由特征可以被配置为在一侧和相对侧之间路由电信号。 第一管芯，第二管芯和桥可以嵌入电绝缘材料中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US12142568B2

公开(公告)日：2024-11-12

申请号：US18139275

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Kevin McCarthy ,  Leigh M. Tribolet ,  Debendra Mallik ,  Ravindranath V. Mahajan ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US12061371B2

公开(公告)日：2024-08-13

申请号：US17131621

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Nitin Deshpande ,  Omkar Karhade ,  Ravindranath V. Mahajan

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/367 ,  H01L25/16

CPC classification number: G02B6/4292 ,  G02B6/423 ,  G02B6/4243 ,  G02B6/4268 ,  H01L23/3675 ,  H01L24/16 ,  H01L25/167 ,  H01L2224/16145

Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.