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    WAFER LEVEL PACKAGING OF REDUCED-HEIGHT INFRARED DETECTORS
    2.
    发明申请
    WAFER LEVEL PACKAGING OF REDUCED-HEIGHT INFRARED DETECTORS 审中-公开
    降低高度红外探测器的水平包装

    公开(公告)号：US20150358558A1

    公开(公告)日：2015-12-10

    申请号：US14728967

    申请日：2015-06-02

    Applicant: FLIR Systems, Inc.

    Inventor： Tiahaar Kurtheru Clayton McKenzie ,  Richard E. Bornfreund ,  Devin Leonard ,  Gregory A. Carlson

    IPC: H04N5/33 ,  H01L21/66 ,  H01L21/78 ,  H01L27/146

    CPC classification number: H01L21/78 ,  H01L21/67092 ,  H01L21/681 ,  H01L21/76251 ,  H01L27/14618 ,  H01L27/14649 ,  H01L27/14687 ,  Y10T83/533

    Abstract: Systems and methods may be provided for generating reduced-height circuit packages such as infrared detector packages. An alignment and dicing system may include an infrared camera that captures images of alignment marks of a wafer assembly through a lid wafer of the wafer assembly, a light source that illuminates the alignment marks through the lid wafer, and dicing equipment that dices the wafer assembly based on infrared images captured using the infrared camera. The light source may illuminate the alignment marks through the lid wafer by providing light such as infrared light to the wafer assembly through optics of the infrared camera. The infrared camera may capture images of alignment marks formed on a detector wafer of the wafer assembly or on an interior or lower surface of the lid wafer through the lid wafer. The dicing equipment may be aligned with the wafer assembly based on the captured images.

    Abstract translation: 可以提供系统和方法来产生诸如红外检测器封装的减小电路封装。 对准和切割系统可以包括红外相机，其通过晶片组件的盖晶片捕获晶片组件的对准标记的图像，通过盖晶片照亮对准标记的光源，以及切割晶片组件的切割设备 基于使用红外摄像机捕获的红外图像。 光源可以通过红外照相机的光学器件通过向晶片组件提供诸如红外光的光来通过盖晶片照亮对准标记。 红外相机可以通过盖晶片捕获形成在晶片组件的检测器晶片上的对准标记的图像或盖晶片的内表面或下表面上的图像。 切片设备可以基于所捕获的图像与晶片组件对准。

    DEPOSITION SYSTEMS AND METHODS
    3.
    发明申请
    DEPOSITION SYSTEMS AND METHODS 有权
    沉积系统和方法

    公开(公告)号：US20150284838A1

    公开(公告)日：2015-10-08

    申请号：US14745246

    申请日：2015-06-19

    Applicant: FLIR Systems, Inc.

    Inventor： Tommy Marx ,  Richard E. Bornfreund ,  Yaroslava Petraitis ,  James L. Dale

    IPC: C23C14/00 ,  C23C14/08 ,  H01J37/34 ,  C23C14/34

    CPC classification number: C23C14/0042 ,  C23C14/0063 ,  C23C14/08 ,  C23C14/083 ,  C23C14/3485 ,  H01J37/3411 ,  H01J37/3429 ,  H01J37/3467 ,  H01J2237/3323

    Abstract: A system is disclosed, including a processing chamber for a deposition process; a cathode within the chamber, configured to introduce a sputter gas and a reactive gas adjacent to a target; a substrate holder, disposed opposite the cathode within the processing chamber, configured to secure a substrate to receive a deposition from the target; and a control system configured to monitor a target voltage and to control a flow rate of the reactive gas to maintain the target voltage within a desired range during the deposition process. Methods and devices for deposition processes are also disclosed.

    Abstract translation: 公开了一种系统，包括用于沉积工艺的处理室; 室内的阴极，被配置为引入与靶相邻的溅射气体和反应气体; 在所述处理室内与所述阴极相对设置的衬底保持器，被配置为固定衬底以接收来自所述靶的沉积; 以及控制系统，其被配置为监测目标电压并且控制所述反应气体的流量以在所述沉积过程期间将所述目标电压维持在期望范围内。 还公开了沉积工艺的方法和装置。

    Method and systems for coupling semiconductor substrates
    4.
    发明授权
    Method and systems for coupling semiconductor substrates 有权

    公开(公告)号：US10971540B2

    公开(公告)日：2021-04-06

    申请号：US15287636

    申请日：2016-10-06

    Applicant: FLIR Systems, Inc.

    Inventor： Richard E. Bornfreund ,  Joseph H. Durham

    IPC: H01L27/146 ,  H01L21/027 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/544

    Abstract: Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process. The bump contacts may be indium bumps. The indium bumps may be formed by depositing a sheet of indium onto a surface of a device substrate, depositing and patterning a layer of photoresist over the indium layer, and selectively etching the indium layer to the surface of the substrate using the patterned photoresist layer to form the indium bumps. The substrate may be an infrared detector substrate. The infrared detector substrate may be coupled to a readout integrated circuit substrate using the bumps.

    Wafer level packaging of reduced-height infrared detectors
    8.
    发明授权
    Wafer level packaging of reduced-height infrared detectors 有权

    公开(公告)号：US10153204B2

    公开(公告)日：2018-12-11

    申请号：US14728967

    申请日：2015-06-02

    Applicant: FLIR Systems, Inc.

    Inventor： Tiahaar Kurtheru Clayton McKenzie ,  Richard E. Bornfreund ,  Devin Leonard ,  Gregory A. Carlson

    IPC: H01L21/78 ,  H01L27/146 ,  H01L21/68 ,  H01L21/67

    Abstract: Systems and methods may be provided for generating reduced-height circuit packages such as infrared detector packages. An alignment and dicing system may include an infrared camera that captures images of alignment marks of a wafer assembly through a lid wafer of the wafer assembly, a light source that illuminates the alignment marks through the lid wafer, and dicing equipment that dices the wafer assembly based on infrared images captured using the infrared camera. The light source may illuminate the alignment marks through the lid wafer by providing light such as infrared light to the wafer assembly through optics of the infrared camera. The infrared camera may capture images of alignment marks formed on a detector wafer of the wafer assembly or on an interior or lower surface of the lid wafer through the lid wafer. The dicing equipment may be aligned with the wafer assembly based on the captured images.

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