公开(公告)号：US20210327795A1

公开(公告)日：2021-10-21

申请号：US17360701

申请日：2021-06-28

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

IPC分类号： H01L23/498 ,  H01L21/68 ,  H01L21/48 ,  H01L23/00

摘要： The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

公开(公告)号：US20190317285A1

公开(公告)日：2019-10-17

申请号：US16473216

申请日：2017-09-12

申请人： Intel Corporation

发明人： Shawna M. LIFF ,  Henning BRAUNISCH ,  Timothy A. GOSSELIN ,  Prasanna RAGHAVAN ,  Yikang DENG ,  Zhiguo QIAN

IPC分类号： G02B6/42 ,  F21V8/00 ,  G02B6/293

摘要： An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.

公开(公告)号：US20180374804A1

公开(公告)日：2018-12-27

申请号：US15774958

申请日：2015-12-26

申请人： Intel Corporation

发明人： Yu Amos ZHANG ,  Gabriel S. REGALADO ,  Zhiguo QIAN ,  Kemal AYGUN

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01P3/06 ,  H01P11/00

摘要： A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.

公开(公告)号：US20180331043A1

公开(公告)日：2018-11-15

申请号：US15774257

申请日：2015-12-26

申请人： Intel Corporation

发明人： Yu Amos ZHANG ,  Zhiguo QIAN ,  Kemal AYGUN ,  Yidnekachew S. MEKONNEN ,  Gregorio R. MURTAGIAN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Jeff C. MORRISS

IPC分类号： H01L23/538 ,  H01L23/66 ,  H01L23/552

CPC分类号： H01L23/5384 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L24/00 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

摘要： A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.

公开(公告)号：US20240355745A1

公开(公告)日：2024-10-24

申请号：US18759008

申请日：2024-06-28

申请人： Intel Corporation

发明人： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC分类号： H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20220093516A1

公开(公告)日：2022-03-24

申请号：US17540141

申请日：2021-12-01

申请人： Intel Corporation

发明人： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

摘要： Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20210104476A1

公开(公告)日：2021-04-08

申请号：US16596383

申请日：2019-10-08

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Cemil GEYIK ,  Jiwei SUN ,  Gang DUAN ,  Kemal AYGÜN

IPC分类号： H01L23/64 ,  H01L23/498

摘要： Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

申请人： Intel Corporation

发明人： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

摘要： Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US20240105572A1

公开(公告)日：2024-03-28

申请号：US18530006

申请日：2023-12-05

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC分类号： H01L23/498

CPC分类号： H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/486 ,  H01L2924/0002

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20230014579A1

公开(公告)日：2023-01-19

申请号：US17956766

申请日：2022-09-29

申请人： Intel Corporation

发明人： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

IPC分类号： H01L23/498

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.