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公开(公告)号：US09779965B2
公开(公告)日：2017-10-03
申请号：US15456767
申请日：2017-03-13
IPC分类号： H01L21/449 , H01L23/00 , H01L25/00 , H01L25/065 , H01L21/762 , H01L21/60
CPC分类号： H01L21/449 , H01L21/76251 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/75 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2021/60195 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13187 , H01L2224/136 , H01L2224/13687 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/48091 , H01L2224/48225 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75343 , H01L2224/75348 , H01L2224/75349 , H01L2224/75744 , H01L2224/75745 , H01L2224/759 , H01L2224/81121 , H01L2224/81193 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81355 , H01L2224/81409 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81801 , H01L2224/81895 , H01L2224/81906 , H01L2224/94 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20301 , H01L2924/20302 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20306 , H01L2924/20307 , H01L2924/01029 , H01L2924/01014 , H01L2924/00012 , H01L2924/014 , H01L2224/8121 , H01L2924/00 , H01L2224/45099 , H01L2224/81 , H01L2924/04941 , H01L2924/04953 , H01L2924/0503 , H01L2924/01013 , H01L2924/0504 , H01L2924/0105 , H01L2924/0502 , H01L2924/0103 , H01L2924/0494 , H01L2924/0104 , H01L2924/0495 , H01L2924/01023 , H01L2924/0496 , H01L2924/01024 , H01L2924/05 , H01L2924/01028 , H01L2924/0543 , H01L2924/0544 , H01L2924/0542 , H01L2924/0534 , H01L2924/0535 , H01L2924/0536 , H01L2924/054 , H01L2924/0463 , H01L2924/0464 , H01L2924/0462 , H01L2924/0454 , H01L2924/0455 , H01L2924/0456 , H01L2924/046 , H01L2924/01105
摘要： A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.
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公开(公告)号：US20170186627A1
公开(公告)日：2017-06-29
申请号：US15456767
申请日：2017-03-13
IPC分类号： H01L21/449 , H01L21/762 , H01L25/00 , H01L25/065 , H01L23/00
CPC分类号： H01L21/449 , H01L21/76251 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/75 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2021/60195 , H01L2224/1134 , H01L2224/1145 , H01L2224/11462 , H01L2224/13082 , H01L2224/131 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13187 , H01L2224/136 , H01L2224/13687 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/48091 , H01L2224/48225 , H01L2224/75251 , H01L2224/75252 , H01L2224/75301 , H01L2224/75343 , H01L2224/75348 , H01L2224/75349 , H01L2224/75744 , H01L2224/75745 , H01L2224/759 , H01L2224/81121 , H01L2224/81193 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81355 , H01L2224/81409 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81801 , H01L2224/81895 , H01L2224/81906 , H01L2224/94 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01047 , H01L2924/01049 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2924/19107 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20301 , H01L2924/20302 , H01L2924/20303 , H01L2924/20304 , H01L2924/20305 , H01L2924/20306 , H01L2924/20307 , H01L2924/01029 , H01L2924/01014 , H01L2924/00012 , H01L2924/014 , H01L2224/8121 , H01L2924/00 , H01L2224/45099 , H01L2224/81 , H01L2924/04941 , H01L2924/04953 , H01L2924/0503 , H01L2924/01013 , H01L2924/0504 , H01L2924/0105 , H01L2924/0502 , H01L2924/0103 , H01L2924/0494 , H01L2924/0104 , H01L2924/0495 , H01L2924/01023 , H01L2924/0496 , H01L2924/01024 , H01L2924/05 , H01L2924/01028 , H01L2924/0543 , H01L2924/0544 , H01L2924/0542 , H01L2924/0534 , H01L2924/0535 , H01L2924/0536 , H01L2924/054 , H01L2924/0463 , H01L2924/0464 , H01L2924/0462 , H01L2924/0454 , H01L2924/0455 , H01L2924/0456 , H01L2924/046 , H01L2924/01105
摘要： A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. A bonding surface of at least one of the first conductive structures and the second conductive structures includes a frangible coating.
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公开(公告)号：US20230380302A1
公开(公告)日：2023-11-23
申请号：US18357814
申请日：2023-07-24
申请人： SeeQC, Inc.
发明人： Daniel Yohannes , Denis Amparo , Oleksandr Chernyashevskyy , Oleg Mukhanov , Mario Renzullo , Andrei Talalaeskii , Igor Vernik , John Vivalda , Jason Walter
CPC分类号： H10N60/815 , H01L24/13 , H01L24/81 , H01L24/05 , H10N60/12 , H10N60/0912 , H01L2924/0495 , H01L2224/0401 , H01L2224/05179 , H01L2224/13083 , H01L2224/13109 , H01L2224/13147 , H01L2224/13166 , H01L2224/13179 , H01L2224/8109 , H01L2224/8112 , H01L2224/81203 , H01L2924/04941
摘要： A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.
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公开(公告)号：US20230210023A1
公开(公告)日：2023-06-29
申请号：US17561439
申请日：2021-12-23
申请人： Intel Corporation
发明人： Hubert C. George , Ravi Pillarisetty , JongSeok Park , Stefano Pellerano , Lester F. Lampert , Thomas F. Watson , Florian Luthi , James S. Clarke
IPC分类号： H01L27/18 , H01L39/22 , H03H7/38 , H01P3/00 , H01L39/24 , H01L39/04 , G06N10/80 , H01L23/00 , H05K1/18
CPC分类号： H01L27/18 , H01L39/228 , H03H7/38 , H01P3/003 , H01L39/24 , H01L39/04 , H01L39/221 , G06N10/80 , H01L24/48 , H01L24/45 , H01L2224/49171 , H01L2224/45144 , H05K2201/10045 , H01L2924/0495 , H01L2224/48225 , H01L2224/45186 , H05K2201/10522 , H05K1/18 , H01L2224/45147 , H01L2224/48153
摘要： Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.
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公开(公告)号：US20240321792A1
公开(公告)日：2024-09-26
申请号：US18607941
申请日：2024-03-18
发明人： Duckgyu Kim
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L2224/02255 , H01L2224/0401 , H01L2224/05166 , H01L2224/05555 , H01L2224/05557 , H01L2924/0495 , H01L2924/0509 , H01L2924/05341
摘要： Provided is a semiconductor package including a semiconductor chip, a pad structure electrically connected to the semiconductor chip, a solder ball spaced apart from the semiconductor chip in a first direction and in contact with the pad structure, and an insulating layer arranged between the semiconductor chip and the pad structure and in contact with the pad structure, wherein the insulating layer includes a first ring-shaped groove having a ring shape surrounding the pad structure, and the first ring-shaped groove is spaced apart from the pad structure.
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公开(公告)号：US11711985B2
公开(公告)日：2023-07-25
申请号：US17472821
申请日：2021-09-13
申请人： SeeQC, Inc.
发明人： Daniel Yohannes , Denis Amparo , Oleksandr Chernyashevskyy , Oleg Mukhanov , Mario Renzullo , Andrei Talalaevskii , Igor Vernik , John Vivalda , Jason Walter
IPC分类号： H01L29/06 , H01L29/08 , H01L31/0256 , H01L39/22 , H10N60/81 , H01L23/00 , H10N60/12 , H10N60/01
CPC分类号： H10N60/815 , H01L24/05 , H01L24/13 , H01L24/81 , H10N60/0912 , H10N60/12 , H01L2224/0401 , H01L2224/05179 , H01L2224/13083 , H01L2224/13109 , H01L2224/13147 , H01L2224/13166 , H01L2224/13179 , H01L2224/8109 , H01L2224/8112 , H01L2224/81203 , H01L2924/0495 , H01L2924/04941
摘要： A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.
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