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公开(公告)号：US20240038633A1
公开(公告)日：2024-02-01
申请号：US17876376
申请日：2022-07-28
IPC分类号： H01L23/473 , H01L23/467 , H01L25/10 , H01L25/18 , H01L23/00 , H01L25/065 , H01L23/32
CPC分类号： H01L23/473 , H01L23/467 , H01L25/105 , H01L25/18 , H01L24/05 , H01L24/08 , H01L25/0657 , H01L23/32 , H01L24/94 , H01L24/80 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2225/06517 , H01L2224/05647 , H01L2224/05686 , H01L2224/05693 , H01L2924/0544 , H01L2924/0504 , H01L2924/059 , H01L2924/05432 , H01L2924/04642 , H01L2224/08245 , H01L2224/94 , H01L2224/80486 , H01L2224/80896 , H01L2224/80895
摘要： Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.
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公开(公告)号：US20230352369A1
公开(公告)日：2023-11-02
申请号：US17731847
申请日：2022-04-28
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L23/481 , H01L23/53238 , H01L21/76898 , H01L21/7684
摘要： Embodiments herein include post-TSV reveal processing methods and devices formed using the methods. In some embodiments, the methods include forming an electrically and thermally conductive layer on the device that may be used as a power/ground connection path or a thermal spreading plane in a device assembly that includes a plurality of interconnected stacked devices.
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公开(公告)号：US20230036441A1
公开(公告)日：2023-02-02
申请号：US17816346
申请日：2022-07-29
IPC分类号： H01L23/00
摘要： A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.
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4.发明申请公开(公告)号：US20220293567A1
公开(公告)日：2022-09-15
申请号：US17681563
申请日：2022-02-25
发明人： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L21/56
摘要： Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
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公开(公告)号：US20220285213A1
公开(公告)日：2022-09-08
申请号：US17825405
申请日：2022-05-26
IPC分类号： H01L21/768 , H01L21/3213 , H01L21/306 , H01L23/00 , H01L21/321 , B24B37/04 , C23F3/00 , H01L21/311 , B81B7/00 , B81C1/00
摘要： Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
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公开(公告)号：US20220246564A1
公开(公告)日：2022-08-04
申请号：US17681019
申请日：2022-02-25
发明人： Guilian Gao , Javier A. DeLaCruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, JR. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US20220189941A1
公开(公告)日：2022-06-16
申请号：US17586236
申请日：2022-01-27
发明人： Paul M. Enquist , Belgacem Haba
IPC分类号： H01L25/00 , H01L25/18 , H01L27/146 , H01L21/822 , H01L23/31 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/07
摘要： Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.
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公开(公告)号：US20220155490A1
公开(公告)日：2022-05-19
申请号：US17587921
申请日：2022-01-28
发明人： Belgacem Haba , Rajesh Katkar , Ilyas MOHAMMED
摘要： Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.
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公开(公告)号：US20220139867A1
公开(公告)日：2022-05-05
申请号：US17452753
申请日：2021-10-28
发明人： Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.
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10.发明授权公开(公告)号：US11296044B2
公开(公告)日：2022-04-05
申请号：US16553535
申请日：2019-08-28
发明人： Guilian Gao , Javier A. Delacruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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