公开(公告)号：US20230352369A1

公开(公告)日：2023-11-02

申请号：US17731847

申请日：2022-04-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Gaius Gillman Fountain, JR. ,  George Carlton Hudson

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L23/53238 ,  H01L21/76898 ,  H01L21/7684

Abstract: Embodiments herein include post-TSV reveal processing methods and devices formed using the methods. In some embodiments, the methods include forming an electrically and thermally conductive layer on the device that may be used as a power/ground connection path or a thermal spreading plane in a device assembly that includes a plurality of interconnected stacked devices.

公开(公告)号：US20220246497A1

公开(公告)日：2022-08-04

申请号：US17646135

申请日：2021-12-27

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Gaius Gillman Fountain, JR. ,  Cyprian Emeka Uzoh ,  George Carlton Hudson ,  John Posthill

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/00

Abstract: A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.