公开(公告)号：US20240038633A1

公开(公告)日：2024-02-01

申请号：US17876376

申请日：2022-07-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Belgacem Haba ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L23/473 ,  H01L23/467 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/32

CPC classification number: H01L23/473 ,  H01L23/467 ,  H01L25/105 ,  H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L23/32 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2225/06517 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/05693 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2924/05432 ,  H01L2924/04642 ,  H01L2224/08245 ,  H01L2224/94 ,  H01L2224/80486 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

公开(公告)号：US20220293567A1

公开(公告)日：2022-09-15

申请号：US17681563

申请日：2022-02-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Thomas Workman ,  Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Gabriel Z. Guevara ,  Joy Watanabe

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

公开(公告)号：US20220285213A1

公开(公告)日：2022-09-08

申请号：US17825405

申请日：2022-05-26

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/306 ,  H01L23/00 ,  H01L21/321 ,  B24B37/04 ,  C23F3/00 ,  H01L21/311 ,  B81B7/00 ,  B81C1/00

Abstract: Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

公开(公告)号：US20220246564A1

公开(公告)日：2022-08-04

申请号：US17681019

申请日：2022-02-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Liang Wang ,  Gaius Gillman Fountain, JR. ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20220139867A1

公开(公告)日：2022-05-05

申请号：US17452753

申请日：2021-10-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.

公开(公告)号：US11296044B2

公开(公告)日：2022-04-05

申请号：US16553535

申请日：2019-08-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Guilian Gao ,  Javier A. Delacruz ,  Shaowu Huang ,  Liang Wang ,  Gaius Gillman Fountain, Jr. ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L23/00

Abstract: Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20220005784A1

公开(公告)日：2022-01-06

申请号：US17320767

申请日：2021-05-14

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Rajesh Katkar ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.

公开(公告)号：US20210375850A1

公开(公告)日：2021-12-02

申请号：US17344100

申请日：2021-06-10

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, JR.

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/18

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US20200321307A1

公开(公告)日：2020-10-08

申请号：US16910432

申请日：2020-06-24

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L21/67 ,  H01L23/48 ,  H01L25/065 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

公开(公告)号：US11257727B2

公开(公告)日：2022-02-22

申请号：US16678037

申请日：2019-11-08

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh ,  Shaowu Huang ,  Guilian Gao ,  Ilyas Mohammed

IPC: H01L23/10 ,  B81C1/00 ,  B81B7/00 ,  H01L23/04 ,  H01L23/053 ,  H01L23/02

Abstract: Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.