公开(公告)号：US20240038633A1

公开(公告)日：2024-02-01

申请号：US17876376

申请日：2022-07-28

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Belgacem Haba ,  Thomas Workman ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L23/473 ,  H01L23/467 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L23/32

CPC classification number: H01L23/473 ,  H01L23/467 ,  H01L25/105 ,  H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L23/32 ,  H01L24/94 ,  H01L24/80 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2225/06517 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/05693 ,  H01L2924/0544 ,  H01L2924/0504 ,  H01L2924/059 ,  H01L2924/05432 ,  H01L2924/04642 ,  H01L2224/08245 ,  H01L2224/94 ,  H01L2224/80486 ,  H01L2224/80896 ,  H01L2224/80895

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

公开(公告)号：US20230036441A1

公开(公告)日：2023-02-02

申请号：US17816346

申请日：2022-07-29

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Belgacem Haba ,  Laura Wills Mirkarimi ,  Christopher Aubuchon ,  Rajesh Katkar

IPC: H01L23/00

Abstract: A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.

公开(公告)号：US20220293567A1

公开(公告)日：2022-09-15

申请号：US17681563

申请日：2022-02-25

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Thomas Workman ,  Guilian Gao ,  Gaius Gillman Fountain, JR. ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Gabriel Z. Guevara ,  Joy Watanabe

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

公开(公告)号：US20220189941A1

公开(公告)日：2022-06-16

申请号：US17586236

申请日：2022-01-27

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. Enquist ,  Belgacem Haba

IPC: H01L25/00 ,  H01L25/18 ,  H01L27/146 ,  H01L21/822 ,  H01L23/31 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

公开(公告)号：US20220155490A1

公开(公告)日：2022-05-19

申请号：US17587921

申请日：2022-01-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Belgacem Haba ,  Rajesh Katkar ,  Ilyas MOHAMMED

IPC: G02B1/10 ,  G02B1/02 ,  G02B27/01

Abstract: Direct-bonded lamination for improved image clarity in optical devices is provided. An example process planarizes and plasma-activates optical surfaces to be laminated together, then forms direct bonds between the two surfaces without an adhesive or adhesive layer. This process provides improved optics with higher image brightness, less light scattering, better resolution, and higher image fidelity. The direct bonds also provide a refractory interface tolerant of much higher temperatures than conventional optical adhesives. The example process can be used to produce many types of improved optical components, such as improved laminated lenses, mirrors, beam splitters, collimators, prism systems, optical conduits, and mirrored waveguides for smartglasses and head-up displays (HUDs), which provide better image quality and elimination of the dark visual lines that are apparent to a human viewer when conventional adhesives are used in conventional lamination.

公开(公告)号：US10784191B2

公开(公告)日：2020-09-22

申请号：US15940273

申请日：2018-03-29

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Shaowu Huang ,  Belgacem Haba ,  Javier A. DeLaCruz

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H03H7/01 ,  H03H1/00

Abstract: A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. A filter circuit can be integrally formed between the first and second elements along the bonding interface.

公开(公告)号：US20220302058A1

公开(公告)日：2022-09-22

申请号：US17836840

申请日：2022-06-09

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Guilian Gao ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

公开(公告)号：US20220122934A1

公开(公告)日：2022-04-21

申请号：US17646238

申请日：2021-12-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Belgacem Haba

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

公开(公告)号：US20210134689A1

公开(公告)日：2021-05-06

申请号：US17146304

申请日：2021-01-11

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Shaowu Huang ,  Javier A. DeLaCruz ,  Liang Wang ,  Rajesh Katkar ,  Belgacem Haba

IPC: H01L23/10 ,  H01L23/66 ,  H01L23/04

Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.

公开(公告)号：US20210098412A1

公开(公告)日：2021-04-01

申请号：US16874527

申请日：2020-05-14

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Belgacem Haba ,  Laura Wills Mirkarimi ,  Javier A. DeLaCruz ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Guilian Gao ,  Thomas Workman

IPC: H01L23/00 ,  H01L23/31

Abstract: A bonded structure can comprise a first element and a second element. The first element has a first dielectric layer including a first bonding surface and at least one first side surface of the first element. The second element has a second dielectric layer including a second bonding surface and at least one second side surface of the second element. The second bonding surface of the second element is directly bonded to the first bonding surface of the first element without an adhesive.