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公开(公告)号：US11296044B2
公开(公告)日：2022-04-05
申请号：US16553535
申请日：2019-08-28
发明人： Guilian Gao , Javier A. Delacruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US10366962B2
公开(公告)日：2019-07-30
申请号：US15385545
申请日：2016-12-20
IPC分类号： H01L21/58 , H01L23/00 , H01L21/20 , H01L21/683 , H01L21/768 , H01L21/822 , H01L23/13 , H01L23/36 , H01L23/48 , H01L23/538 , H01L25/065 , H01L25/16 , H01L25/00 , H01L27/06 , H01L21/762 , H01L21/18 , H01L23/552 , H01L25/18 , H01L27/146
摘要： A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
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公开(公告)号：US20210265227A1
公开(公告)日：2021-08-26
申请号：US17315170
申请日：2021-05-07
发明人： Rajesh Katkar , Laura Wills Mirkarimi , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh
IPC分类号： H01L23/10 , H01L23/00 , H01L21/768
摘要： A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.
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公开(公告)号：US11011418B2
公开(公告)日：2021-05-18
申请号：US16206927
申请日：2018-11-30
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/065 , H01L25/00 , H01L27/06
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
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公开(公告)号：US10896902B2
公开(公告)日：2021-01-19
申请号：US16599744
申请日：2019-10-11
IPC分类号： H01L25/00 , H01L21/67 , H01L21/683 , H01L21/78 , H01L21/66 , H01L25/10 , H01L25/075
摘要： Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.
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公开(公告)号：US10312217B2
公开(公告)日：2019-06-04
申请号：US15205346
申请日：2016-07-08
IPC分类号： H01L23/00 , H01L21/02 , H01L21/20 , H01L21/311 , H01L21/762 , H01L29/06 , H01L21/322 , H01L27/085 , H01L29/16 , H01L25/065 , H01L25/00
摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
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公开(公告)号：US10269708B2
公开(公告)日：2019-04-23
申请号：US15853085
申请日：2017-12-22
IPC分类号： H01L25/065 , H01L21/768 , H01L23/528 , H01L23/522 , H01L25/00 , H01L23/00
摘要： A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
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公开(公告)号：US20220302058A1
公开(公告)日：2022-09-22
申请号：US17836840
申请日：2022-06-09
发明人： Guilian Gao , Bongsub Lee , Gaius Gillman Fountain, Jr. , Cyprian Emeka Uzoh , Laura Wills Mirkarimi , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
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公开(公告)号：US20220285236A1
公开(公告)日：2022-09-08
申请号：US17825240
申请日：2022-05-26
IPC分类号： H01L21/66 , H01L21/768 , H01L23/532 , H01L23/538 , H01L23/522
摘要： Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.
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10.发明授权公开(公告)号：US11011494B2
公开(公告)日：2021-05-18
申请号：US16218769
申请日：2018-12-13
发明人： Guilian Gao , Gaius Gillman Fountain, Jr. , Laura Wills Mirkarimi , Rajesh Katkar , Ilyas Mohammed , Cyprian Emeka Uzoh
IPC分类号： H01L23/42 , H01L23/52 , H01L29/40 , H01L23/00 , H01L23/522 , H01L21/768
摘要： Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
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