公开(公告)号：US20180233484A1

公开(公告)日：2018-08-16

申请号：US15432329

申请日：2017-02-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor structure includes a first die; a second die disposed over or at least partially in contact with the first die; a redistribution layer (RDL) disposed over the second die; a conductive pillar extended between the first die and the RDL; and a molding surrounding the first die, the second die and the conductive pillar, wherein the first die and the RDL are electrically connected by the conductive pillar.

公开(公告)号：US20180166417A1

公开(公告)日：2018-06-14

申请号：US15377192

申请日：2016-12-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099

Abstract: A semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (RDL) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. The molding member does not extend into an interface between the first semiconductor device and the second semiconductor device.

公开(公告)号：US20180166418A1

公开(公告)日：2018-06-14

申请号：US15853522

申请日：2017-12-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A method for preparing a wafer level chip-on-chip semiconductor structure. The semiconductor structure includes a first semiconductor device; at least one conductive member disposed over the first semiconductor device; a second semiconductor device disposed over the first semiconductor device; a molding member disposed over the first semiconductor device; and a redistribution layer (RDL) disposed over the second semiconductor device and the at least one conductive member. The molding member surrounds the second semiconductor device and the at least one conductive member. The molding member does not extend into an interface between the first semiconductor device and the second semiconductor device.

公开(公告)号：US20180374818A1

公开(公告)日：2018-12-27

申请号：US16119572

申请日：2018-08-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L23/00 ,  H01L21/306 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/324

Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

公开(公告)号：US20180233486A1

公开(公告)日：2018-08-16

申请号：US15434569

申请日：2017-02-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/11 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/1712 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0105 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

公开(公告)号：US20180226380A1

公开(公告)日：2018-08-09

申请号：US15853456

申请日：2017-12-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788

Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

公开(公告)号：US20180233480A1

公开(公告)日：2018-08-16

申请号：US15853435

申请日：2017-12-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/324 ,  H01L21/306 ,  H01L21/768

Abstract: The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

公开(公告)号：US20180233479A1

公开(公告)日：2018-08-16

申请号：US15434606

申请日：2017-02-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/83 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05578 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80035 ,  H01L2224/80357 ,  H01L2224/80801 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80935 ,  H01L2224/80986 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2224/034

Abstract: The present disclosure is directed to a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique and a method for preparing the same. The semiconductor devices have conductive portions with higher coefficient of thermal expansion than their dielectric portions. By forming the depression to provide a space for the volume expansion of the conductive portion with higher coefficient of thermal expansion during the subsequent thermal treating process of the fusion bonding, the semiconductor apparatus formed of semiconductor devices by the fusion bonding technique does not exhibit a lateral protrusion into the interface between the two dielectric portions. As a result, the failure of the electrical function due to the lateral protrusion is effectively eliminated.

公开(公告)号：US20180204814A1

公开(公告)日：2018-07-19

申请号：US15853477

申请日：2017-12-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN ,  CHIN-LUNG CHU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: The present disclosure provides a method far preparing a semiconductor package. The semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical hump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

公开(公告)号：US20180190607A1

公开(公告)日：2018-07-05

申请号：US15397044

申请日：2017-01-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： PO-CHUN LIN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/11 ,  H01L25/0655 ,  H01L2224/16012 ,  H01L2224/16104 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029

Abstract: A semiconductor package includes a first device and a bump structure disposed over the first device. In some embodiments, the first device has a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device. In some embodiments, the bump structure is disposed over the first upper surface and extends laterally across the first side of the first device. The lateral extension of the bump structure across the first side of the semiconductor device can contact a corresponding conductor of a laterally adjacent device to implement a lateral signal path between the semiconductor device and the laterally adjacent device in the absence of a redistribution structure corresponding to the redistribution layer.