公开(公告)号：US09013044B2

公开(公告)日：2015-04-21

申请号：US13945392

申请日：2013-07-18

Applicant: Micron Technology Inc.

Inventor： Alan G Wood ,  David R Hembree

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01L23/498

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side thereof; a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate; a dielectric material in the via configured to electrically insulate the wire from the semiconductor substrate; a bonding member bonded to the first end of the wire and to the substrate contact configured to secure the wire to the substrate contact; and a contact on the second end of the wire.

Abstract translation: 用于半导体衬底的通线互连包括从第一侧延伸穿过半导体衬底到第二侧的通孔; 所述通孔中的导线具有第一端，所述第一端具有与所述衬底接触的接合连接，以及靠近所述半导体衬底的第二侧的第二端; 所述通孔中的电介质材料被配置为使所述导线与所述半导体衬底电绝缘; 接合构件，其接合到所述导线的所述第一端和所述衬底接触件，被配置为将所述导线固定到所述衬底接触件; 和电线第二端的触点。

公开(公告)号：US08513797B2

公开(公告)日：2013-08-20

申请号：US13480528

申请日：2012-05-25

Applicant: Alan G. Wood ,  David R. Hembree

Inventor： Alan G. Wood ,  David R. Hembree

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate.

Abstract translation: 半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。 通线互连（TWI）包括穿过基板接触件和基板的通孔，通孔中的压接线接合到基板触点，以及在导线上的接触。 堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。

公开(公告)号：US20120024089A1

公开(公告)日：2012-02-02

申请号：US12920105

申请日：2008-02-29

Applicant: Jeremiah Couey ,  Michael T. Deley ,  Shawn Sarbacker ,  Matthew Odhner

Inventor： Jeremiah Couey ,  Michael T. Deley ,  Shawn Sarbacker ,  Matthew Odhner

IPC: G01N33/00 ,  B23K37/00 ,  B23K20/00

CPC classification number: H01L24/85 ,  B23K20/004 ,  B23K2101/42 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78703 ,  H01L2224/78901 ,  H01L2224/85121 ,  H01L2224/8513 ,  H01L2224/85132 ,  H01L2224/8518 ,  H01L2224/85191 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01049

Abstract: A method of teaching bonding locations of a semiconductor device on a wire bonding machine is provided. The method includes (1) providing the wire bonding machine with position data for (a) bonding locations of a first component of the semiconductor device, and (b) bonding locations of a second component of the semiconductor device; and (2) teaching the bonding locations of the first component of the semiconductor device and the second component of the semiconductor device using a pattern recognition system of the wire bonding machine to obtain more accurate position data for at least a portion of the bonding locations of the first component and the second component. The teaching step is conducted by teaching the bonding locations in the order in which they are configured to be wire bonded on the wire bonding machine.

Abstract translation: 提供了一种在引线接合机上教导半导体器件的接合位置的方法。 该方法包括：（1）为引线接合机提供位置数据，用于（a）半导体器件的第一部件的接合位置，和（b）半导体器件的第二部件的接合位置; 以及（2）使用引线接合机的图案识别系统来教导半导体器件的第一部件和半导体器件的第二部件的接合位置，以获得更准确的位置数据，用于至少一部分接合位置 第一组件和第二组件。 该教导步骤是通过在引线接合机上按照被配置为引线键合的顺序来教导接合位置进行的。

公开(公告)号：US20110114704A1

公开(公告)日：2011-05-19

申请号：US12924607

申请日：2010-09-30

Applicant: Kenji Sugawara ,  Yong Chen

Inventor： Kenji Sugawara ,  Yong Chen

IPC: B23K31/12 ,  B23K3/00 ,  B23K20/00 ,  B23K31/02

CPC classification number: H01L24/85 ,  B23K20/007 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2224/78301 ,  H01L2224/85121 ,  H01L2224/85148 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A bonding apparatus provided with a control unit capable of controlling the position of the central axis of a bonding tool in the X direction and the Y direction based on an image of a pad acquired with a camera and an offset amount, the apparatus including: an outline obtaining unit for obtaining each of the sides of the pad and an outline of a pressure-bonded ball by processing the image acquired with the camera; a gap length obtaining unit for obtaining gap lengths between the respective sides of the pad and the outline of the pressure-bonded ball; and an offset correcting unit for correcting the offset amount based on the gap lengths obtained by the gap obtaining unit.

Abstract translation: 一种接合装置，其具有控制单元，该控制单元能够基于利用摄像机获取的垫的图像和偏移量来控制接合工具在X方向和Y方向上的中心轴的位置，该装置包括： 轮廓获取单元，用于通过处理由相机获取的图像来获得垫的每个侧面和压接球的轮廓; 间隙长度获得单元，用于获得垫的各个侧面与压接球的轮廓之间的间隙长度; 以及偏移校正单元，用于基于由间隙获得单元获得的间隙长度来校正偏移量。

公开(公告)号：US07931186B2

公开(公告)日：2011-04-26

申请号：US12093403

申请日：2007-03-13

Applicant: Michael T. Deley ,  Peter M. Lister ,  Deepak Sood ,  Zhijie Wang

Inventor： Michael T. Deley ,  Peter M. Lister ,  Deepak Sood ,  Zhijie Wang

IPC: B23K31/00 ,  B23K11/00

CPC classification number: B23K20/004 ,  B23K2101/40 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/78901 ,  H01L2224/85121 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  Y10S228/904 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05556 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of teaching an eyepoint for a wire bonding operation is provided. The method includes (1) selecting a group of shapes from a region of a semiconductor device for use as an eyepoint, and (2) teaching the eyepoint to a wire bonding machine using at least one of (a) a sample semiconductor device, or (b) predetermined data related to the semiconductor device. The teaching step includes defining locations of each of the shapes with respect to one another.

Abstract translation: 提供了一种教导用于引线键合操作的眼点的方法。 该方法包括：（1）从半导体器件的区域中选择一组形状用作眼点，以及（2）使用（a）样品半导体器件或 （b）与半导体器件相关的预定数据。 教学步骤包括相对于彼此定义每个形状的位置。

公开(公告)号：US07573142B2

公开(公告)日：2009-08-11

申请号：US11407273

申请日：2006-04-19

Applicant: Seok-Han Park ,  Joo-Sung Park ,  Dong-Hyun Han

Inventor： Seok-Han Park ,  Joo-Sung Park ,  Dong-Hyun Han

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/85 ,  H01L2223/54473 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/85121 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An alignment key structure in a semiconductor device is provided. The alignment key structure includes an insulation layer formed on a substrate, and a passivation layer pattern formed on the insulation layer. The insulation layer includes a plurality of metal wirings. The passivation layer pattern includes a first opening that exposes at least one of the metal wirings. Moreover, the first opening has a width which is narrower than a width of the exposed metal wiring.

Abstract translation: 提供半导体器件中的对准键结构。 对准键结构包括形成在基板上的绝缘层和形成在绝缘层上的钝化层图案。 绝缘层包括多个金属配线。 钝化层图案包括露出至少一个金属布线的第一开口。 此外，第一开口的宽度比暴露的金属布线的宽度窄。

公开(公告)号：US20080042247A1

公开(公告)日：2008-02-21

申请号：US11859776

申请日：2007-09-23

Applicant: Alan Wood ,  David Hembree

Inventor： Alan Wood ,  David Hembree

IPC: H01L23/495

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

Abstract translation: 半导体部件包括具有基板接触的半导体基板和与该基板接触部接合的贯通线互连（TWI）。 通线互连（TWI）包括通过基板接触和基板的通孔，连接到基板触点的通孔中的导线和线上的触点。 堆叠的半导体部件包括半导体衬底和堆叠在衬底上并结合到衬底上的通孔互连的第二半导体衬底。 一种用于制造具有通孔布线的半导体部件的方法包括以下步骤：提供具有基板接触的半导体基板，通过基板接触形成通孔，并且部分地穿过基板，将导线放置在通孔中，将导线接合到 衬底接触，然后从第二侧使衬底变薄以暴露线上的接触。 用于制造半导体部件的系统包括被配置为将导线放置在通路中并且在导线和基板接触之间形成接合连接的接合毛细管。

公开(公告)号：US20070126091A1

公开(公告)日：2007-06-07

申请号：US11296057

申请日：2005-12-07

Applicant: Alan Wood ,  David Hembree

Inventor： Alan Wood ,  David Hembree

IPC: H01L23/495

CPC classification number: H01L23/02 ,  B33Y70/00 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/6834 ,  H01L2224/02333 ,  H01L2224/02335 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/49429 ,  H01L2224/78301 ,  H01L2224/85001 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85121 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85951 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00015 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012

Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire. A system for fabricating the semiconductor component includes a bonding capillary configured to place the wire in the via, and to form a bonded connection between the wire and the substrate contact.

公开(公告)号：US07209583B2

公开(公告)日：2007-04-24

申请号：US10959242

申请日：2004-10-06

Applicant: Satoshi Enokido ,  Kenji Sugawara

Inventor： Satoshi Enokido ,  Kenji Sugawara

IPC: G06K9/00

CPC classification number: H01L24/78 ,  B23K20/004 ,  B23K37/0408 ,  B23K2101/40 ,  H01L23/544 ,  H01L24/85 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/78301 ,  H01L2224/85121 ,  H01L2224/8513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/04953 ,  H01L2224/48 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: With an assumption that the three data of the position (X1, Y1) of the first positioning pattern 202 and position (X2, Y2) of the second positioning pattern 212 of the reference chip 200, and the position (X3, Y3) of the first positioning pattern 232 of the bonding object chip 230, as well as the length L of a line segment connecting (X1, Y1) and (X2, Y2), and the angle θ2 of this line segment with respect to the X axis, are known, the coordinates (X4, Y4) of the center position of the imaging range 250 that is to be imaged next is determined by detecting the inclination-angle Δθ of the first positioning pattern 232 of the bonding object chip 230. Furthermore, the imaging range can be narrowed and the second positioning pattern 252 can be captured by increasing the precision of Δθ.

Abstract translation: 假设第一定位图案202的位置（X 1> 1，Y 1> 1）的三个数据和位置（X <2> 2 参考芯片200的第二定位图案212的第二定位图案212的位置（X 3/3，Y 3 3），以及第一定位 接合对象芯片230的图案232以及连接（X 1> 1，Y 1 1）和（X 2> 2）的线段的长度L， SUB>，Y 2 2）和该线段相对于X轴的角度θ2 <2>是已知的，坐标（X <4> 通过检测接合对象芯片230的第一定位图案232的倾斜角Deltatheta来确定下一个要被成像的成像范围250的中心位置的SUB>，Y 4 4 _{。 此外，可以缩小成像范围，并且可以通过增加Deltatheta的精度来捕获第二定位图案252。}

公开(公告)号：US20050167471A1

公开(公告)日：2005-08-04

申请号：US10959242

申请日：2004-10-06

Applicant: Satoshi Enokido ,  Kenji Sugawara

Inventor： Satoshi Enokido ,  Kenji Sugawara

IPC: H01L21/60 ,  B23K20/00 ,  B23K31/12 ,  B23K37/04

CPC classification number: H01L24/78 ,  B23K20/004 ,  B23K37/0408 ,  B23K2101/40 ,  H01L23/544 ,  H01L24/85 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2224/78301 ,  H01L2224/85121 ,  H01L2224/8513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/04953 ,  H01L2224/48 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: With an assumption that the three data of the position (X1, Y1) of the first positioning pattern 202 and position (X2, Y2) of the second positioning pattern 212 of the reference chip 200, and the position (X3, Y3) of the first positioning pattern 232 of the bonding object chip 230, as well as the length L of a line segment connecting (X1, Y1) and (X2, Y2), and the angle θ2 of this line segment with respect to the X axis, are known, the coordinates (X4, Y4) of the center position of the imaging range 250 that is to be imaged next is determined by detecting the inclination-angle Δθ of the first positioning pattern 232 of the bonding object chip 230. Furthermore, the imaging range can be narrowed and the second positioning pattern 252 can be captured by increasing the precision of Δθ.

Abstract translation: 假设第一定位图案202的位置（X 1> 1，Y 1> 1）的三个数据和位置（X <2> 2 参考芯片200的第二定位图案212的第二定位图案212的位置（X 3/3，Y 3 3），以及第一定位 接合对象芯片230的图案232以及连接（X 1> 1，Y 1 1）和（X 2> 2）的线段的长度L， SUB>，Y 2 2）和该线段相对于X轴的角度θ2 <2>是已知的，坐标（X <4> 通过检测接合对象芯片230的第一定位图案232的倾斜角Deltatheta来确定下一个要被成像的成像范围250的中心位置的SUB>，Y 4 4 _{。 此外，可以缩小成像范围，并且可以通过增加Deltatheta的精度来捕获第二定位图案252。}