公开(公告)号：US08836055B2

公开(公告)日：2014-09-16

申请号：US13250078

申请日：2011-09-30

Applicant: Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Lung Yuan Pan ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L31/115

CPC classification number: H01G5/18 ,  B81B3/001 ,  B81B2201/0221 ,  H01L28/60

Abstract: A device includes a micro-electro-mechanical system (MEMS) device, which includes a movable element and a fixed element. The movable element and the fixed element form two capacitor plates of a capacitor, with an air-gap between the movable element and the fixed element acting as a capacitor insulator of the capacitor. At least one of the movable element and the fixed element has a rugged surface.

Abstract translation: 一种装置包括微电子机械系统（MEMS）装置，其包括可移动元件和固定元件。 可移动元件和固定元件形成电容器的两个电容器板，可动元件和固定元件之间的气隙用作电容器的电容器绝缘体。 可移动元件和固定元件中的至少一个具有粗糙的表面。

公开(公告)号：US08790946B2

公开(公告)日：2014-07-29

申请号：US13365043

申请日：2012-02-02

Applicant: Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Li-Cheng Chu ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

IPC: H01L21/52

CPC classification number: B23K20/002 ,  B23K20/023

Abstract: A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.

Abstract translation: 一种方法包括通过共晶接合将第一接合层结合到第二接合层。 接合步骤包括将第一接合层和第二接合层加热至高于第一接合层和第二接合层的共晶温度的温度，并进行泵送循环。 泵送循环包括施加第一力以将第一接合层和第二接合层相互挤压。 在施加第一力的步骤之后，施加比第一力小的第二力以将第一接合层和第二接合层相互挤压。 在施加第二力的步骤之后，施加比第二力高的第三力以将第一接合层和第二接合层相互挤压。

公开(公告)号：US08647962B2

公开(公告)日：2014-02-11

申请号：US12729911

申请日：2010-03-23

Applicant: Martin Liu ,  Richard Chu ,  Hung Hua Lin ,  Hsin-Ting Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Richard Chu ,  Hung Hua Lin ,  Hsin-Ting Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L21/76

CPC classification number: H01L25/162 ,  B81B2207/012 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/187 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Abstract translation: 本公开提供了一种接合多个基板的方法。 在一个实施例中，第一衬底包括第一接合层。 第二基板包括第二接合层。 第一接合层包括硅; 第二结合层包括铝。 第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。 还提供了一种在衬底之间具有接合区域的器件。 接合区域包括在包括硅的层和包括铝的层之间的界面。

公开(公告)号：US20130285180A1

公开(公告)日：2013-10-31

申请号：US13458812

申请日：2012-04-27

Applicant: Tzu-Jui Wang ,  Szu-Ying Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Ping-Yin Liu ,  Lan-Lin Chao

Inventor： Tzu-Jui Wang ,  Szu-Ying Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Ping-Yin Liu ,  Lan-Lin Chao

IPC: H01L31/0232 ,  H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14683 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/1469 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias.

Abstract translation: 背面照明图像传感器包括光电二极管和位于第一芯片中的第一晶体管，其中第一晶体管电耦合到光电二极管。 背面照明图像传感器还包括形成在第二芯片中的第二晶体管和形成在第三芯片中的多个逻辑电路，其中第二芯片堆叠在第一芯片上，第三芯片堆叠在第二芯片上。 逻辑电路，第二晶体管和第一晶体管通过多个焊盘和通孔彼此耦合。

公开(公告)号：US20130284885A1

公开(公告)日：2013-10-31

申请号：US13457637

申请日：2012-04-27

Applicant: Szu-Ying Chen ,  Ping-Yin Liu ,  Calvin Yi-Ping Chao ,  Tzu-Jui Wang ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Lan-Lin Chao

Inventor： Szu-Ying Chen ,  Ping-Yin Liu ,  Calvin Yi-Ping Chao ,  Tzu-Jui Wang ,  Jen-Cheng Liu ,  Dun-Nian Yaung ,  Lan-Lin Chao

IPC: H01L27/146

CPC classification number: H01L27/1469 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.

Abstract translation: 公开了用于封装具有专用集成电路（ASIC）的背面照明（BSI）图像传感器或传感器装置的方法和装置。 根据实施例，传感器设备可以与ASIC面对面地结合在一起，而不使用载体晶片，其中传感器的相应接合焊盘与ASIC的接合焊盘对准并且结合在一起，以一对一 一个时尚。 传感器的像素列可以共享由共享的金属间线路连接不良的键。 接合焊盘可以具有不同的尺寸并且被配置成不同的行以彼此不相交。 可以添加附加的虚拟焊盘以增加传感器和ASIC之间的接合。

公开(公告)号：US20130208371A1

公开(公告)日：2013-08-15

申请号：US13372141

申请日：2012-02-13

Applicant: Hung-Hua LIN ,  Li-Cheng CHU ,  Ming-Tung WU ,  Yuan-Chih HSIEH ,  Lan-Lin CHAO ,  Chia-Shiung TSAI

Inventor： Hung-Hua LIN ,  Li-Cheng CHU ,  Ming-Tung WU ,  Yuan-Chih HSIEH ,  Lan-Lin CHAO ,  Chia-Shiung TSAI

IPC: G02B5/08 ,  B05D3/10 ,  B05D5/06

CPC classification number: G01N21/55 ,  G01N21/01 ,  G01N21/253 ,  G01N27/327 ,  G01N33/483 ,  G01N2021/0106 ,  G01N2201/0636

Abstract: A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.

Abstract translation: 形成包括衬底的一部分的生物感测结构的方法被凹进以在衬底中形成多个台面。 多个台面中的每一个具有顶表面和侧壁表面。 第一光反射层沉积在每个台面的顶表面和侧壁表面上。 在第一光反射层的第一部分上形成填充材料。 沉积在填充材料上的停止层和第一光反射层的第二部分。 牺牲层形成在停止层上并且被平坦化地暴露停止层。 在停止层和第一光反射层中形成第一开口。 第二光反射层沉积在第一开口上。 在第二光反射层中形成第二开口。

公开(公告)号：US20120238091A1

公开(公告)日：2012-09-20

申请号：US13481550

申请日：2012-05-25

Applicant: Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer.

Abstract translation: 本公开提供了通孔结构及其制造方法的各种实施例。 在一个实例中，用于形成通孔结构的方法包括在半导体衬底中形成通孔，其中通孔的通孔侧壁由半导体衬底限定; 在所述通孔侧壁上形成介电层; 从所述通孔侧壁的一部分去除所述介电层; 以及形成导电层以填充所述通孔，其中所述导电层设置在所述电介质层和所述通孔侧壁的所述部分之上。 在一个实例中，电介质层是氧化物层。

公开(公告)号：US08207595B2

公开(公告)日：2012-06-26

申请号：US12898408

申请日：2010-10-05

Applicant: Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L29/40

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

Abstract translation: 半导体器件包括衬底晶片，覆盖衬底晶片的电介质层，电介质层中的图案化导体层和覆盖导体层的第一势垒层。 硅顶片结合到电介质层。 通孔通过顶部晶片和介电层的一部分形成到第一阻挡层。 侧壁电介质层沿通孔的内壁形成，与顶部晶片相邻，距离顶部晶片的上表面一定距离，形成侧壁电介质层的肩部。 在侧壁电介质层的内侧形成侧壁阻挡层，将通孔从第一阻挡层衬套到顶部晶片的上表面。 导电层填充通孔，并且在导电层，侧壁阻挡层和顶部晶片上形成顶部阻挡层。

公开(公告)号：US20120091598A1

公开(公告)日：2012-04-19

申请号：US12905358

申请日：2010-10-15

Applicant: Chun-Ren Cheng ,  Yi-Hsien Chang ,  Allen Timothy Chang ,  Ching-Ray Chen ,  Li-Cheng Chu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao

Inventor： Chun-Ren Cheng ,  Yi-Hsien Chang ,  Allen Timothy Chang ,  Ching-Ray Chen ,  Li-Cheng Chu ,  Hung-Hua Lin ,  Yuan-Chih Hsieh ,  Lan-Lin Chao

IPC: H01L23/544 ,  H01L21/71

CPC classification number: B81C1/0038

Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.

Abstract translation: 提供了一种包括透明基板的装置。 在透明基板上设置不透明层。 设置在不透明层上的导电层。 不透明层和导电层形成处理层，其可用于在制造工艺期间检测和/或对准透明晶片。 在一个实施例中，导电层包括高度掺杂的硅层。 在一个实施例中，不透明层包括金属。 在实施例中，设备可以包括MEMs设备。

公开(公告)号：US20080188055A1

公开(公告)日：2008-08-07

申请号：US11586528

申请日：2006-10-26

Applicant: Yu-Jen Wang ,  Chia-Shiung Tsai ,  Yeur-Luen Tu ,  Lan-Lin Chao ,  Chih-Ta Wu ,  Hsing-Lien Lin ,  Chung Chien Wang

Inventor： Yu-Jen Wang ,  Chia-Shiung Tsai ,  Yeur-Luen Tu ,  Lan-Lin Chao ,  Chih-Ta Wu ,  Hsing-Lien Lin ,  Chung Chien Wang

IPC: H01L21/02

CPC classification number: H01L28/60 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.

Abstract translation: 一种制造半导体器件的方法包括形成具有金属有机化学气相沉积（MOCVD）下电极和原子层沉积（ALD）上电极的金属 - 绝缘体 - 金属（MIM）器件。