公开(公告)号：US08173518B2

公开(公告)日：2012-05-08

申请号：US12414910

申请日：2009-03-31

Applicant: Martin Liu ,  Alex Hsu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Alex Hsu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L21/30

CPC classification number: H01L27/1469 ,  H01L21/76256 ,  H01L27/14634 ,  H01L27/1464

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合 将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

公开(公告)号：US20100248446A1

公开(公告)日：2010-09-30

申请号：US12414861

申请日：2009-03-31

Applicant: Martin Liu ,  Chung-Yi Yu ,  Che Ying Hsu ,  Yeur-Luen Tu ,  Da-Hsiang Chou ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Chung-Yi Yu ,  Che Ying Hsu ,  Yeur-Luen Tu ,  Da-Hsiang Chou ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  B25B11/00

CPC classification number: H01L21/6838 ,  H01L21/304

Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.

Abstract translation: 提供了一种保持装置的装置和方法。 该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。 该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

公开(公告)号：US20100248414A1

公开(公告)日：2010-09-30

申请号：US12414910

申请日：2009-03-31

Applicant: Martin Liu ,  Alex Hsu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Alex Hsu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L31/02 ,  H01L21/762 ,  H01L21/304

CPC classification number: H01L27/1469 ,  H01L21/76256 ,  H01L27/14634 ,  H01L27/1464

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合 将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

公开(公告)号：US08964413B2

公开(公告)日：2015-02-24

申请号：US12765412

申请日：2010-04-22

Applicant: Martin Liu

Inventor： Martin Liu

IPC: H02M3/335 ,  H02M1/42 ,  H02M3/337 ,  H02M1/00

CPC classification number: H02M1/4225 ,  H02M3/3378 ,  H02M2001/0058 ,  Y02B70/126 ,  Y02B70/1433 ,  Y02B70/1491 ,  Y02P80/112

Abstract: A resonant converter comprising: a controllable current source; a resonant tank circuit coupled to the current source; and an isolated buck-type converter coupled to the resonant tank circuit, the isolated buck-type converter having an output, wherein the resonant tank circuit enables switches in the isolated buck-type converter to switch under soft-switching conditions. In some embodiments, the controllable current source is a switch-mode-type current source. In some embodiments, the isolated buck-type converter comprises a half-bridge converter. In some embodiments, the isolated buck-type converter comprises a full-bridge converter. In some embodiments, the isolated buck-type converter comprises a push-pull converter.

Abstract translation: 一种谐振变换器，包括：可控电流源; 耦合到电流源的谐振回路; 以及耦合到所述谐振回路的隔离降压型转换器，所述隔离降压型转换器具有输出，其中所述谐振回路使得所述隔离降压型转换器中的开关在软开关条件下切换。 在一些实施例中，可控电流源是开关模式型电流源。 在一些实施例中，隔离降压型转换器包括半桥转换器。 在一些实施例中，隔离降压型转换器包括全桥转换器。 在一些实施例中，隔离降压型转换器包括推挽转换器。

公开(公告)号：US08648468B2

公开(公告)日：2014-02-11

申请号：US12846504

申请日：2010-07-29

Applicant: Richard Chu ,  Martin Liu ,  Chia-Hua Chu ,  Yuan-Chih Hsieh ,  Chung-Hsien Lin ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Mingo Liu

Inventor： Richard Chu ,  Martin Liu ,  Chia-Hua Chu ,  Yuan-Chih Hsieh ,  Chung-Hsien Lin ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Mingo Liu

IPC: H01L23/48

CPC classification number: H01L24/94 ,  B81B2207/015 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/0771 ,  H01L23/481 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum -based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract translation: 提供晶圆级封装。 该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。 所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。 其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。

公开(公告)号：US08598687B2

公开(公告)日：2013-12-03

申请号：US13481574

申请日：2012-05-25

Applicant: Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L29/40

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

公开(公告)号：US20120235300A1

公开(公告)日：2012-09-20

申请号：US13481574

申请日：2012-05-25

Applicant: Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

Inventor： Yuan-Chih Hsieh ,  Richard Chu ,  Ming-Tung Wu ,  Martin Liu ,  Lan-Lin Chao ,  Chia-Shiung Tsai

IPC: H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.

Abstract translation: 本公开提供了通孔结构及其制造方法的各种实施例。 在一个示例中，通孔结构包括具有由半导体衬底限定的通孔侧壁表面的通孔。 通孔侧壁表面具有第一部分和第二部分。 在通路侧壁表面的第一部分上的通路中设置导电层，并且介电层设置在通孔侧壁表面的第二部分上。 电介质层设置在通孔侧壁表面的第二部分和导电层之间。 在一个实例中，电介质层是氧化物层。

公开(公告)号：US08048807B2

公开(公告)日：2011-11-01

申请号：US12205269

申请日：2008-09-05

Applicant: Ming Chyi Liu ,  Yao Fei Chuang ,  Martin Liu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

Inventor： Ming Chyi Liu ,  Yao Fei Chuang ,  Martin Liu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L27/14698 ,  H01L21/30604 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643

Abstract: Provided is a method for fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a backside, where active or passive devices are formed in the front side, rotating the semiconductor substrate, and etching the backside of the semiconductor substrate by introducing a first etchant while the substrate is rotated, the first etchant including an R—COOH.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，其中在前侧形成有源或无源器件，旋转半导体衬底，并通过引入半导体衬底蚀刻半导体衬底的背面 在衬底旋转的同时第一蚀刻剂，第一蚀刻剂包括R-COOH。

公开(公告)号：US20110233621A1

公开(公告)日：2011-09-29

申请号：US12729911

申请日：2010-03-23

Applicant: Martin Liu ,  Richard Chu ,  Hung-Hua Lin ,  H. T. Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Richard Chu ,  Hung-Hua Lin ,  H. T. Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

IPC: H01L27/04 ,  H01L21/77 ,  H01L29/84

CPC classification number: H01L25/162 ,  B81B2207/012 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/187 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Abstract translation: 本公开提供了一种接合多个基板的方法。 在一个实施例中，第一衬底包括第一接合层。 第二基板包括第二接合层。 第一接合层包括硅; 第二结合层包括铝。 第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。 还提供了一种在衬底之间具有接合区域的器件。 接合区域包括在包括硅的层和包括铝的层之间的界面。

公开(公告)号：US08647962B2

公开(公告)日：2014-02-11

申请号：US12729911

申请日：2010-03-23

Applicant: Martin Liu ,  Richard Chu ,  Hung Hua Lin ,  Hsin-Ting Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

Inventor： Martin Liu ,  Richard Chu ,  Hung Hua Lin ,  Hsin-Ting Huang ,  Jung-Huei Peng ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chun-Wen Cheng ,  Chia-Shiung Tsai

IPC: H01L21/30 ,  H01L21/00 ,  H01L21/46 ,  H01L21/76

CPC classification number: H01L25/162 ,  B81B2207/012 ,  B81C1/00269 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/187 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.

Abstract translation: 本公开提供了一种接合多个基板的方法。 在一个实施例中，第一衬底包括第一接合层。 第二基板包括第二接合层。 第一接合层包括硅; 第二结合层包括铝。 第一基板和第二基板被接合形成在第一接合层和第二接合层之间具有界面的接合区域。 还提供了一种在衬底之间具有接合区域的器件。 接合区域包括在包括硅的层和包括铝的层之间的界面。