公开(公告)号：US20180254267A1

公开(公告)日：2018-09-06

申请号：US15971274

申请日：2018-05-04

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kenichiro SATO

IPC: H01L25/18 ,  H01L21/67 ,  H01L23/495 ,  H01L25/07 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/67121 ,  H01L21/67259 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/05 ,  H01L24/09 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/77 ,  H01L24/84 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/77272 ,  H01L2224/77702 ,  H01L2224/77705 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80815 ,  H01L2224/85121 ,  H01L2224/85136 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/172 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

公开(公告)号：US09991242B2

公开(公告)日：2018-06-05

申请号：US14620184

申请日：2015-02-11

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kenichiro Sato

IPC: H01L23/00 ,  H01L25/18 ,  H01L21/67 ,  H01L23/495 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L25/18 ,  H01L21/67121 ,  H01L21/67259 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/05 ,  H01L24/09 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/77 ,  H01L24/84 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/77272 ,  H01L2224/77702 ,  H01L2224/77705 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80815 ,  H01L2224/85121 ,  H01L2224/85136 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/172 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/207

Abstract: A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US20170062381A1

公开(公告)日：2017-03-02

申请号：US15308544

申请日：2015-05-08

Applicant: ROHM CO., LTD.

Inventor： Kazuya IKOMA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L24/85 ,  B23K20/10 ,  B23K20/1205 ,  B23K20/129 ,  H01L21/4825 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48456 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/78314 ,  H01L2224/78315 ,  H01L2224/78343 ,  H01L2224/7855 ,  H01L2224/78705 ,  H01L2224/78756 ,  H01L2224/83801 ,  H01L2224/85047 ,  H01L2224/85136 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2924/014

Abstract: A manufacturing method for a wire bonding structure of the present invention includes a step of preparing a wire made of Cu and a step of joining the wire to a first joining target formed on an electronic device. Before the joining step, the wire has an outer circumferential surface and a withdrawn surface. The withdrawn surface is withdrawn toward a central axis of the wire from the outer circumferential surface. In the joining step, ultrasonic vibration is applied to the wire in a state in which the withdrawn surface is pressed against the first joining target.

Abstract translation: 本发明的引线接合结构体的制造方法包括：制备由Cu制成的线的步骤和将导线接合到形成在电子器件上的第一接合目标的步骤。 在接合步骤之前，电线具有外圆周表面和退出表面。 退出的表面从外周面朝着线的中心轴线退出。 在接合步骤中，在退避表面被压靠在第一接合对象上的状态下，将超声波振动施加于线。

公开(公告)号：US20150255444A1

公开(公告)日：2015-09-10

申请号：US14620184

申请日：2015-02-11

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kenichiro SATO

IPC: H01L25/18 ,  H01L21/67 ,  H01L23/00 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L25/18 ,  H01L21/67121 ,  H01L21/67259 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/05 ,  H01L24/09 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/77 ,  H01L24/84 ,  H01L24/85 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40227 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73271 ,  H01L2224/77272 ,  H01L2224/77702 ,  H01L2224/77705 ,  H01L2224/80121 ,  H01L2224/80136 ,  H01L2224/80815 ,  H01L2224/85121 ,  H01L2224/85136 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/172 ,  H01L2924/17724 ,  H01L2924/17747 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/207

Abstract: A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.

Abstract translation: 半导体器件具有设置在具有导电图案的绝缘电路板和端子之间的多个小尺寸半导体芯片。 半导体器件在半导体芯片的定位方面表现出高精度。 半导体器件包括具有导电图案的绝缘电路板，​​通过第一接合材料连接到导电图案的矩形形状的第一半导体芯片，具有矩形形状的第二半导体芯片，设置在与第一接合材料分离的导电图案上 半导体芯片，并且通过第二接合材料连接到导电图案，以及设置在第一半导体芯片和第二半导体芯片上方的端子，通过第三接合材料连接到第一半导体芯片，并且通过第二接合材料连接到第二半导体芯片 第四连接材料。 端子在第一半导体芯片和第二半导体芯片之间的位置之上具有通孔。