公开(公告)号：US20240162181A1

公开(公告)日：2024-05-16

申请号：US18486831

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun Jae KIM ,  Sun Kyoung SEO ,  Cha Jea JO

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L24/03 ,  H01L24/11 ,  H01L24/33 ,  H01L2223/54426 ,  H01L2224/0346 ,  H01L2224/03466 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/0532 ,  H01L2924/0543 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/059 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package comprising: a first semiconductor chip extending in each of first and second directions that intersect each other; a second semiconductor chip on the first semiconductor chip in a third direction perpendicular to the first and second directions, wherein the second semiconductor chip includes a first area and a second area that is adjacent to and extends around the first area; and a bump structure and a conductive material layer between the first and second semiconductor chips, wherein the conductive material layer is on the bump structure, wherein the bump structure includes a first bump structure overlapping the first area in the third direction, and a second bump structure overlapping the second area in the third direction, wherein the first and second bump structures are spaced apart from each other, and a thickness of the second bump structure is larger than a thickness of the first bump structure.

公开(公告)号：US20190295998A1

公开(公告)日：2019-09-26

申请号：US16439409

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Hyeok IM ,  Hee Seok LEE ,  Taek Kyun SHIN ,  Cha Jea JO

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/13 ,  H01L23/31 ,  H01L21/683 ,  H01L29/06 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor device package and a semiconductor apparatus are provided. The semiconductor device includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the second portion is inserted into the first interposer hole.

公开(公告)号：US20180315740A1

公开(公告)日：2018-11-01

申请号：US15849767

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Hyeok IM ,  Hee Seok LEE ,  Taek Kyun SHIN ,  Cha Jea JO

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device package includes a first semiconductor package, a second semiconductor package, and an interposer between the first and second semiconductor packages. The first semiconductor package includes a first semiconductor package substrate and a first semiconductor chip. The second semiconductor package includes a second semiconductor package substrate and a second semiconductor chip. The interposer electrically connects the first semiconductor package to the second semiconductor package and includes a first interposer hole passing through the interposer. The first semiconductor chip includes a second portion which protrudes from a first portion, and the first portion is inserted into the first interposer hole.