公开(公告)号：US12131943B2

公开(公告)日：2024-10-29

申请号：US18359412

申请日：2023-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sai-Hooi Yeong ,  Yen-Chieh Huang

IPC分类号： H01L29/66 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/764 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.

公开(公告)号：US20240357828A1

公开(公告)日：2024-10-24

申请号：US18760013

申请日：2024-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-Chen Wang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC分类号： H10B51/20 ,  H01L29/417 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC分类号： H10B51/20 ,  H01L29/41741 ,  H01L29/41775 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.

公开(公告)号：US20240347632A1

公开(公告)日：2024-10-17

申请号：US18756682

申请日：2024-06-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/786 ,  H10B51/20

CPC分类号： H01L29/78391 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/78693 ,  H10B51/20

摘要： A semiconductor device is described. The semiconductor device includes a blocking layer disposed on a channel of a substrate, a first seed layer disposed on the blocking layer, and a ferroelectric gate layer formed on the first seed layer. The first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), in which O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.

公开(公告)号：US12119402B2

公开(公告)日：2024-10-15

申请号：US18308791

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L29/786 ,  H10B51/20

CPC分类号： H01L29/78391 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/78693 ,  H10B51/20

摘要： A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

公开(公告)号：US12058869B2

公开(公告)日：2024-08-06

申请号：US17837982

申请日：2022-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Bo-Feng Young ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC分类号： H10B51/20 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B51/30 ,  H10B51/40

CPC分类号： H10B51/20 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0688 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H10B10/12 ,  H10B51/30 ,  H10B51/40

摘要： The present disclosure provides a semiconductor structure, including a first layer including a logic device, a second layer over the first layer including a first type memory device, and a though silicon via (TSV) electrically connecting the logic device and the first type memory device.

公开(公告)号：US12041783B2

公开(公告)日：2024-07-16

申请号：US17880803

申请日：2022-08-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC分类号： H10B51/30 ,  H01L29/66 ,  H01L29/786 ,  H10B51/20

CPC分类号： H10B51/30 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H10B51/20

摘要： Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.

公开(公告)号：US20240138153A1

公开(公告)日：2024-04-25

申请号：US18178529

申请日：2023-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Meng-Han Lin ,  Chia-En Huang ,  Sai-Hooi Yeong

IPC分类号： H10B51/30

CPC分类号： H10B51/30

摘要： A ferroelectric memory device and a memory array are provided. The ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. The source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. The channel layer has a bottom planar portion and wall portions. The bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. The work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. The ferroelectric layer separates the channel layer from the work function layer.

公开(公告)号：US11942177B2

公开(公告)日：2024-03-26

申请号：US17572370

申请日：2022-01-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ta Yu ,  Chia-En Huang ,  Sai-Hooi Yeong ,  Yih Wang ,  Yi-Ching Liu

IPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14

摘要： One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

公开(公告)号：US11776855B2

公开(公告)日：2023-10-03

申请号：US18080677

申请日：2022-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L21/764

CPC分类号： H01L21/823431 ,  H01L21/3086 ,  H01L21/764 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US11749370B2

公开(公告)日：2023-09-05

申请号：US17198898

申请日：2021-03-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chao-I Wu ,  Shih-Lien Linus Lu ,  Sai-Hooi Yeong

IPC分类号： G11C29/38 ,  G11C16/08 ,  G06F11/20 ,  G11C16/26 ,  G11C16/10

CPC分类号： G11C29/38 ,  G06F11/2094 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

摘要： A method of testing a three dimensional (3D) memory cell array includes writing data to each layer of memory cells in the 3D memory cell array, simultaneously performing a read operation of each memory cell in at least a first pillar of the 3D memory cell array, determining whether a memory cell in the 3D memory cell array has failed in response to the read operation, and replacing at least one failed memory cell in the 3D memory cell array with a spare memory cell in response to determining that the memory cell in the 3D memory cell array has failed. The first pillar includes memory cells on each corresponding layer of the 3D memory cell array.