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1.发明公开公开(公告)号：US20230369420A1
公开(公告)日：2023-11-16
申请号：US18357264
申请日：2023-07-24
发明人： Yen-Chieh Huang , Po-Ting Lin , Song-Fu Liao , Hai-Ching Chen , Chung-Te Lin
CPC分类号： H01L29/40111 , H01L29/6684 , H01L29/78391 , H10B51/00
摘要： In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
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2.发明公开公开(公告)号：US20230247841A1
公开(公告)日：2023-08-03
申请号：US17591174
申请日：2022-02-02
发明人： Yen-Chieh Huang , Po-Ting Lin , Song-Fu Liao , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L27/1159 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L27/1159 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L29/0847 , H01L29/1033 , H01L29/6656 , H01L29/42324
摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.
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公开(公告)号：US20240008287A1
公开(公告)日：2024-01-04
申请号：US17857047
申请日：2022-07-04
发明人： Po-Ting Lin , Wei-Chih Wen , Kai-Wen Cheng , Wu-Wei Tsai , Yu-Ming Hsiang , Yan-Yi Chen , Hai-Ching Chen , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L27/11514 , H01L29/51 , H01L29/66 , H01L29/78 , H01L23/522 , H01L23/528
CPC分类号： H01L27/11514 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L23/5226 , H01L23/5283
摘要： A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.
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公开(公告)号：US11670715B2
公开(公告)日：2023-06-06
申请号：US17460096
申请日：2021-08-27
发明人： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/78 , H01L29/786 , H01L27/11597 , H01L29/49
CPC分类号： H01L29/78391 , H01L27/11597 , H01L29/4908 , H01L29/78642 , H01L29/78693
摘要： A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.
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公开(公告)号：US20230069233A1
公开(公告)日：2023-03-02
申请号：US17460096
申请日：2021-08-27
发明人： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/78 , H01L29/786 , H01L29/49 , H01L27/11597
摘要： A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.
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公开(公告)号：US20240347632A1
公开(公告)日：2024-10-17
申请号：US18756682
申请日：2024-06-27
发明人： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/78 , H01L29/49 , H01L29/786 , H10B51/20
CPC分类号： H01L29/78391 , H01L29/4908 , H01L29/78642 , H01L29/78693 , H10B51/20
摘要： A semiconductor device is described. The semiconductor device includes a blocking layer disposed on a channel of a substrate, a first seed layer disposed on the blocking layer, and a ferroelectric gate layer formed on the first seed layer. The first seed layer is arranged to increase a ratio of (O+T+C)/(O+T+C+M), in which O is the orthorhombic fraction of the ferroelectric gate layer, T is the tetragonal fraction of the ferroelectric gate layer, C is the cubic fraction of the ferroelectric gate layer, and M is the monoclinic fraction of the ferroelectric gate layer.
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公开(公告)号：US12119402B2
公开(公告)日：2024-10-15
申请号：US18308791
申请日：2023-04-28
发明人： Yen-Chieh Huang , Po-Ting Lin , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/78 , H01L29/49 , H01L29/786 , H10B51/20
CPC分类号： H01L29/78391 , H01L29/4908 , H01L29/78642 , H01L29/78693 , H10B51/20
摘要： A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.
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8.发明授权公开(公告)号：US11810956B2
公开(公告)日：2023-11-07
申请号：US17570028
申请日：2022-01-06
发明人： Yen-Chieh Huang , Po-Ting Lin , Song-Fu Liao , Hai-Ching Chen , Chung-Te Lin
CPC分类号： H01L29/40111 , H01L29/6684 , H01L29/78391 , H10B51/00
摘要： In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.
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公开(公告)号：US20230262989A1
公开(公告)日：2023-08-17
申请号：US17673059
申请日：2022-02-16
发明人： Yen-Chieh Huang , Po-Ting Lin , Song-Fu Liao , Hai-Ching Chen , Sai-Hooi Yeong , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L27/1159 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786 , H01L29/66
CPC分类号： H01L27/1159 , H01L29/0665 , H01L29/6684 , H01L29/42392 , H01L29/66742 , H01L29/78391 , H01L29/78618 , H01L29/78696
摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a first electrode structure disposed in a substrate. A first ferroelectric structure is disposed on a first side of the first electrode structure. A channel structure is disposed on a first side of the first ferroelectric structure. The channel structure includes a plurality of individual channel structures and a plurality of insulator structures. The plurality of individual channel structures and the plurality of insulator structures are alternately stacked. A pair of source/drain (S/D) structures are disposed on the first side of the first ferroelectric structure. The pair of S/D structures extend vertically through the channel structure, and the first electrode structure is disposed laterally between the S/D structures of the pair of S/D structures.
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10.发明公开公开(公告)号：US20240145571A1
公开(公告)日：2024-05-02
申请号：US18150259
申请日：2023-01-05
发明人： Po-Ting Lin , Yu-Ming Hsiang , Wei-Chih Wen , Yin-Hao Wu , Wu-Wei Tsai , Hai-Ching Chen , Yu-Ming Lin , Chung-Te Lin
CPC分类号： H01L29/516 , H01L21/02178 , H01L21/02194 , H01L21/0228 , H01L29/66969 , H01L29/78391 , H10B51/30
摘要： In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
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