- 专利标题： Using embedded switches for reducing capacitive loading on a memory system
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申请号： US17572370申请日： 2022-01-10
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公开(公告)号： US11942177B2公开(公告)日： 2024-03-26
- 发明人: Chia-Ta Yu , Chia-En Huang , Sai-Hooi Yeong , Yih Wang , Yi-Ching Liu
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- 当前专利权人地址： TW Hsinchu
- 代理机构： FOLEY & LARDNER LLP
- 主分类号： G11C7/02
- IPC分类号： G11C7/02 ; G11C7/12 ; G11C7/18 ; G11C8/08 ; G11C8/14
摘要：
One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.
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