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公开(公告)号：US20240397725A1
公开(公告)日：2024-11-28
申请号：US18202541
申请日：2023-05-26
Inventor： Chun-Chieh Lu , Yu-Ming Lin , Kuo-Chang Chiang , Yu-Chuan Shih , Huai-Ying Huang
Abstract: A field-effect transistor (FET), selectively switchable between first and second states, includes: source and drain regions and a channel region disposed therebetween; a gate arranged to selectively receive a bias voltage which switches the FET between the first and second states; a memory structure between the gate and the channel region, structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric, both portions being polarized in a first direction when the FET is in the first state; and a depolarization dielectric layer disposed proximate to the memory structure. When the FET is set to the first state, the depolarization dielectric layer destabilizes a polarization of the second portion of the memory structure while maintaining a polarization of the first portion.
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公开(公告)号：US20240206185A1
公开(公告)日：2024-06-20
申请号：US18591047
申请日：2024-02-29
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC: H10B51/20 , H01L21/02 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
CPC classification number: H10B51/20 , H01L21/02565 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
Abstract: The present disclosure relates to an integrated chip device. The integrated chip device includes a plurality of conductive lines disposed over a substrate. The plurality of conductive lines are stacked onto one another and are separated from one another by dielectric layers interleaved between adjacent ones of the plurality of conductive lines. A ferroelectric layer is along sidewalls of the plurality of conductive lines and the dielectric layers. The ferroelectric layer separates a channel layer from the plurality of conductive lines. A species is disposed within the ferroelectric layer. The species has a concentration that decreases from the channel layer towards a surface of the ferroelectric layer that faces away from the channel layer.
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公开(公告)号：US11950427B2
公开(公告)日：2024-04-02
申请号：US17869824
申请日：2022-07-21
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC: H01L21/00 , H01L21/02 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/20 , H10B51/30
CPC classification number: H10B51/20 , H01L21/02565 , H01L21/383 , H01L21/425 , H01L21/477 , H01L29/24 , H10B51/30
Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
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公开(公告)号：US20230371257A1
公开(公告)日：2023-11-16
申请号：US18359181
申请日：2023-07-26
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
IPC: H01L29/76 , H01L23/522
CPC classification number: H10B43/27 , H01L23/5221 , H10B41/10 , H10B41/27 , H10B43/10
Abstract: A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.
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公开(公告)号：US20230328997A1
公开(公告)日：2023-10-12
申请号：US18336105
申请日：2023-06-16
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
CPC classification number: H10B51/20 , H01L21/02565 , H01L29/24 , H10B51/30
Abstract: The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
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Patent Agency Ranking
公开(公告)号：US11581336B2
公开(公告)日：2023-02-14
申请号：US16892038
申请日：2020-06-03
Inventor： Yu-Ming Lin , Chun-Chieh Lu , Bo-Feng Young , Han-Jong Chia , Chenchen Jacob Wang , Sai-Hooi Yeong
IPC: H01L27/11597 , G11C7/18 , H01L27/1159 , H01L27/11587 , G11C8/14
Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.
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公开(公告)号：US20220359570A1
公开(公告)日：2022-11-10
申请号：US17869824
申请日：2022-07-21
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
IPC: H01L27/11597 , H01L29/24 , H01L27/1159 , H01L21/477 , H01L21/425 , H01L21/383 , H01L21/02
Abstract: A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.
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8.发明申请公开(公告)号：US20180350898A1
公开(公告)日：2018-12-06
申请号：US16100532
申请日：2018-08-10
Inventor： Chewn-Pu Jou , Chih-Hsin Ko , Po-Wen Chiu , Chao-Ching Cheng , Chun-Chieh Lu , Chi-Feng Huang , Huan-Neng Chen , Fu-Lung Hsueh , Clement Hsingjen Wann
IPC: H01L49/02 , H01L23/532 , H01G4/005 , H01G4/008 , H01L23/528 , H01L23/522 , H01L21/768
CPC classification number: H01L28/75 , C01B2204/04 , C01B2204/32 , H01G4/005 , H01G4/008 , H01L21/76852 , H01L23/5223 , H01L23/5226 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L23/53266 , H01L23/53276 , H01L2924/0002 , H01L2924/00
Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
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公开(公告)号：US12224351B2
公开(公告)日：2025-02-11
申请号：US18352230
申请日：2023-07-13
Inventor： Chao-Ching Cheng , Chun-Chieh Lu , Hung-Li Chiang , Tzu-Chiang Chen
IPC: H01L29/786 , H01L29/66
Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
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公开(公告)号：US12193241B2
公开(公告)日：2025-01-07
申请号：US18336105
申请日：2023-06-16
Inventor： Chun-Chieh Lu , Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chih-Yu Chang
Abstract: The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.
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