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公开(公告)号：US20240365689A1
公开(公告)日：2024-10-31
申请号：US18764340
申请日：2024-07-04
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： H10N70/231 , G11C13/0004 , H10N70/8828
摘要： The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
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公开(公告)号：US20240315152A1
公开(公告)日：2024-09-19
申请号：US18669541
申请日：2024-05-21
发明人： Hung-Li Chiang , Jer-Fu Wang , Chao-Ching Cheng , Tzu-Chiang Chen
CPC分类号： H10N70/8413 , H10B63/20 , H10N70/011 , H10N70/231 , H10N70/826
摘要： A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
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公开(公告)号：US12069970B2
公开(公告)日：2024-08-20
申请号：US17672695
申请日：2022-02-16
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： H10N70/231 , G11C13/0004 , H10N70/8828
摘要： The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
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公开(公告)号：US12062696B2
公开(公告)日：2024-08-13
申请号：US18352249
申请日：2023-07-14
CPC分类号： H01L29/1033 , H01L23/36 , H01L29/0607 , H01L29/0669 , H01L29/66477 , H01L29/78
摘要： A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
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公开(公告)号：US20240260279A1
公开(公告)日：2024-08-01
申请号：US18610689
申请日：2024-03-20
CPC分类号： H10B63/80 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , H10B63/20 , H10N70/011 , G11C2013/0045 , G11C2013/0078
摘要： The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.
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公开(公告)号：US20240250122A1
公开(公告)日：2024-07-25
申请号：US18624386
申请日：2024-04-02
IPC分类号： H01L29/06 , H01L21/308 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/308 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages
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公开(公告)号：US11848242B2
公开(公告)日：2023-12-19
申请号：US17706362
申请日：2022-03-28
IPC分类号： H01L29/76 , H01L29/94 , H01L31/112 , H01L21/8238 , H01L29/06 , H01L29/78 , H01L27/092 , H01L29/66
CPC分类号： H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L27/0924 , H01L29/0673 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
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8.发明公开公开(公告)号：US20230263078A1
公开(公告)日：2023-08-17
申请号：US17672695
申请日：2022-02-16
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： H01L45/06 , H01L45/144 , G11C13/0004
摘要： The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
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公开(公告)号：US11575046B2
公开(公告)日：2023-02-07
申请号：US17011274
申请日：2020-09-03
发明人： I-Sheng Chen , Tzu-Chiang Chen , Cheng-Hsien Wu , Ling-Yen Yeh , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L21/768 , H01L27/092 , B82Y10/00 , H01L29/423 , H01L29/775 , H01L29/08 , H01L29/786 , H01L29/40 , H01L27/06 , H01L21/822 , H01L29/06
摘要： A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.
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公开(公告)号：US11367482B2
公开(公告)日：2022-06-21
申请号：US17016398
申请日：2020-09-10
发明人： Carlos H. Diaz , Hung-Li Chiang , Tzu-Chiang Chen , Yih Wang
摘要： A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.
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