-
公开(公告)号：US20240250122A1
公开(公告)日：2024-07-25
申请号：US18624386
申请日：2024-04-02
IPC分类号： H01L29/06 , H01L21/308 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0649 , H01L21/308 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L27/0886 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages
-
公开(公告)号：US11848242B2
公开(公告)日：2023-12-19
申请号：US17706362
申请日：2022-03-28
IPC分类号： H01L29/76 , H01L29/94 , H01L31/112 , H01L21/8238 , H01L29/06 , H01L29/78 , H01L27/092 , H01L29/66
CPC分类号： H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L27/0924 , H01L29/0673 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
-
公开(公告)号：US11575046B2
公开(公告)日：2023-02-07
申请号：US17011274
申请日：2020-09-03
发明人： I-Sheng Chen , Tzu-Chiang Chen , Cheng-Hsien Wu , Ling-Yen Yeh , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L21/768 , H01L27/092 , B82Y10/00 , H01L29/423 , H01L29/775 , H01L29/08 , H01L29/786 , H01L29/40 , H01L27/06 , H01L21/822 , H01L29/06
摘要： A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.
-
公开(公告)号：US11043561B2
公开(公告)日：2021-06-22
申请号：US16723559
申请日：2019-12-20
发明人： I-Sheng Chen , Cheng-Hsien Wu , Chih Chieh Yeh , Yee-Chia Yeo
IPC分类号： H01L29/10 , H01L29/06 , H01L29/165 , H01L29/423 , H01L29/66 , H01L29/786 , H01L29/78 , H01L27/088 , H01L27/092 , H01L21/8238
摘要： A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.
-
公开(公告)号：US10522622B2
公开(公告)日：2019-12-31
申请号：US15979123
申请日：2018-05-14
IPC分类号： H01L29/76 , H01L31/113 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/423 , H01L21/8234
摘要： A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.
-
公开(公告)号：US10269965B1
公开(公告)日：2019-04-23
申请号：US15793521
申请日：2017-10-25
发明人： I-Sheng Chen , Tzu-Chiang Chen , Cheng-Hsien Wu , Ling-Yen Yeh , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L21/82 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L21/768 , H01L27/088
摘要： A multi-gate semiconductor device includes a substrate, a stacked wire structure disposed over the substrate, a gate over the stacked wire structure, and at least a first spacer disposed over two sidewalls of the gate. The gate further includes a gate conductive structure wrapping the stacked wire structure and a gate dielectric layer sandwiched between the gate conductive structure and the stacked wire structure. Further, sidewalls of the gate conductive structure are in contact with the first spacer.
-
公开(公告)号：US11923413B2
公开(公告)日：2024-03-05
申请号：US17666051
申请日：2022-02-07
发明人： Ta-Chun Lin , Kuo-Hua Pan , Jhon-Jhy Liaw , Chao-Ching Cheng , Hung-Li Chiang , Shih-Syuan Huang , Tzu-Chiang Chen , I-Sheng Chen , Sai-Hooi Yeong
IPC分类号： H01L29/76 , H01L21/02 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/94
CPC分类号： H01L29/0673 , H01L21/02603 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
-
公开(公告)号：US11923252B2
公开(公告)日：2024-03-05
申请号：US17159823
申请日：2021-01-27
发明人： Sai-Hooi Yeong , Bo-Feng Young , Chi-On Chui , Chih-Chieh Yeh , Cheng-Hsien Wu , Chih-Sheng Chang , Tzu-Chiang Chen , I-Sheng Chen
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823885 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.
-
公开(公告)号：US11908749B2
公开(公告)日：2024-02-20
申请号：US18057741
申请日：2022-11-21
发明人： Yi-Jing Lee , Ya-Yun Cheng , Hau-Yu Lin , I-Sheng Chen , Chia-Ming Hsu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L23/00 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L21/321 , H01L21/02 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/02068 , H01L21/28088 , H01L21/321 , H01L27/0922 , H01L29/4966 , H01L29/66545
摘要： A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.
-
公开(公告)号：US11894438B2
公开(公告)日：2024-02-06
申请号：US17353460
申请日：2021-06-21
发明人： Yee-Chia Yeo , Sung-Li Wang , Chi On Chui , Jyh-Cherng Sheu , Hung-Li Chiang , I-Sheng Chen
IPC分类号： H01L29/45 , H01L21/8238 , H01L27/092 , H01L21/8234 , H01L23/522 , H01L27/088 , H01L29/08 , H01L29/417 , H01L29/78
CPC分类号： H01L29/45 , H01L21/823425 , H01L21/823814 , H01L21/823821 , H01L23/5226 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/0847 , H01L29/41791 , H01L29/7851 , H01L21/823807 , H01L29/456 , H01L2029/7858
摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.022 秒)
